# Set input low or high in Quartus

I have created a 4 bit register in VHDL, within Quartus. Normally, I connect each of my inputs to one of the dip switch pins or push button pins in the "pin planner" for my particular development board. Sometimes I have input logic that, for testing purposes, always need to stay high or low. In the example below, the clearN(active low) input needs to be simply held high without wasting one of my dip pins. Is there some pin that I can connect it to that will just provide VCC or ground depending on what I want?

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY REG_4_MAR_SAP_1 IS

GENERIC(
size: INTEGER:=3);

PORT(
LmN, Clk, clearN: IN STD_LOGIC;
D: IN STD_LOGIC_VECTOR(size DOWNTO 0);
Q: OUT STD_LOGIC_VECTOR(size DOWNTO 0));

END REG_4_MAR_SAP_1;

ARCHITECTURE Structural_REG_4_MAR_SAP_1 OF REG_4_MAR_SAP_1 IS

Signal E: STD_LOGIC;

COMPONENT D_FF_W_ENABLE_CLEAR PORT(
D, E, ClearN, Clk: IN STD_LOGIC;
Q: BUFFER STD_LOGIC);
END COMPONENT;

COMPONENT NOT_1 PORT(
In0: IN STD_LOGIC;
Out0: OUT STD_LOGIC);
END COMPONENT;

BEGIN

Reg4: FOR k IN size DOWNTO 0 GENERATE
FlipFlop: D_FF_W_ENABLE_CLEAR PORT MAP(D(k), E, ClearN, clk, Q(k));
END GENERATE Reg4;

U1: NOT_1 PORT MAP(LmN, E);

END Structural_REG_4_MAR_SAP_1;


## 1 Answer

If you develop real device, then if you already know that some signal is always tied to the specific level you just remove it from input pins and assign this signal the level within the design.

If you perform simulation then you can assign steady specific level to the port input pin using simulation tool.

• Yes I understand. I just found it odd that i can assign pins to DIPs or Push buttons that provide power or ground but I can't assign a pin that just gives you power or ground without the switch or button. – BPoy Aug 22 '18 at 12:07