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Can anybody explain this code to me?

module test(clk,a);
  input clk;
  output a;
  reg temp;
  initial begin
  temp  <= 1'b1;
  always @(posedge clk)
    a <= ~temp;
  end
endmodule

I wanted to write code such that for every clock cycle the value of 'a' alternated between '0' and '1'.

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module test(clk,temp);
  input clk;
  output reg temp;
  initial temp = 1'b1;
  always @(posedge clk)
    temp <= ~temp;
endmodule

Issue in your code that each clock you assign a with inverted value of temp which stays constant; and also put all this stuff into initial block. Use temp in the code above, you do not need any additional register.

Edit: agreed with comment to another answer poster, initial is used for simulation, within real hardware you will need reset input signal

module test(clk,temp,reset_n);
  input clk;
  input reset_n;
  output reg temp;
  always @(posedge clk or negedge reset_n)
    if(!reset_n) temp <= 1'b1;
    else temp <= ~temp;
endmodule
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  • \$\begingroup\$ i agree that temp will be constant but , the code it self its saying syntax error..any idea \$\endgroup\$ – Sai Siril Aug 22 '18 at 9:33
  • \$\begingroup\$ @SaiSiril Your always needs to be outside the initial block. \$\endgroup\$ – awjlogan Aug 22 '18 at 9:41
  • \$\begingroup\$ @SaiSiril would help if you tell where syntax error is, but I guess it is in initial line because there must be = instead of <=. I edited my answer. \$\endgroup\$ – Anonymous Aug 22 '18 at 10:46
  • \$\begingroup\$ 'Initial' blocks may be acceptable for FPGAs, depending on what tools you use. In any case it doesn't really matter - this circuit will work whatever the initial state is. \$\endgroup\$ – Jules Aug 22 '18 at 15:30
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If my verilog is not too rusty.

You start the module and define all the inputs, outputs and signals you are planning to use. Which is this part:

input clk;
output a;
reg temp;

You start the module with

Initial begin

You define your temp signal as a one. 1'b1 is Verilog syntax for a constant value that is a one bit number expressed in binary format with a value of one. A bit value of zero would be expressed as 1'b0.

 temp  <= 1'b1;

at the next part you say, every time the clock has a positive edge toggle the bit which is in temp and write it to a The ~ symbol represents bitwise negation. Each bit in the value is toggled

always @(posedge clk)
a <= ~temp;
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  • 2
    \$\begingroup\$ It will also not work as expected: think what happens to temp. The initial is also problematic as it's not realisable in hardware (maybe in an FPGA). It should be done with a reset input. \$\endgroup\$ – awjlogan Aug 22 '18 at 9:07
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initial blocks only execute once at time=0. if you want to use intitial, use it, but put your always@ elsewhere, outside the initial block, which is defined by begin... end

and, yes, as others say, initial is for simulation only... for real HW, use a reset to "initialize" a register

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It helps other to explain both what you expected (you did), and what you actually saw (syntax error).

The problem with your code is you have an always construct where only procedural statements are allowed. The always construct instantiates a process to execute procedural code, but it is not a procedural statement itself. The initial construct also creates a process, but is not a procedural statement. You may want to read this discussion.

The other problem with your code is you are trying to make procedural assignments to the wire a, which is not allowed. See this post for a complete explanation.

What you wanted to write is:

module test(input wire clk,
            output reg a);
  initial a = 1;
  always @(posedge clk)
    a <= ~a;
  end
endmodule

The next issue is if you want to synthesize this code into hardware, does your tool support an initial state for a, or will you need a separate reset signal to do that.

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