It helps other to explain both what you expected (you did), and what you actually saw (syntax error).
The problem with your code is you have an
always construct where only procedural statements are allowed. The
always construct instantiates a process to execute procedural code, but it is not a procedural statement itself. The
initial construct also creates a process, but is not a procedural statement. You may want to read this discussion.
The other problem with your code is you are trying to make procedural assignments to the wire
a, which is not allowed. See this post for a complete explanation.
What you wanted to write is:
module test(input wire clk,
output reg a);
initial a = 1;
always @(posedge clk)
a <= ~a;
The next issue is if you want to synthesize this code into hardware, does your tool support an initial state for
a, or will you need a separate reset signal to do that.