How does the AXI-Interconnect know where to route the data?

Im interested in where exactly the Addresses (BASE_ADDR) set in the "Address Editor" of a Vivado Block Design come into play in the FPGA-Part. I have multiple Blocks with AXI-Lite connected to a Zynq via an AXI-Interconnect, which works fine. But i want to know how:

To my current understanding, the routing must be somewhere in the AXI-Interconnect-IP-Block, however i can not see how it knows where to route the bus as "Customize IP" shows nothing related to the Addresses. It just seems to magically connect everything correctly...

So how does it work?

Edit: For clarification - this is how the part of my system looks like:

                       ______________
|              |---------- Block 1 (AXI-Lite)
|    AXI       |---------- Block 2 (AXI-Lite)
Zynq (AXI Bus) -------| Interconnect |---------- Block 3 (AXI-Lite)
|              |---------- Block 4 (AXI-Lite)
|______________|---------- Block 5 (AXI-Lite)


The Zynq itself is not relevant in this picture, there is just a full AXI-Bus on the left and multiple AXI-Lite-Blocks on the right, which can have Address-Ranges set in the "Address Editor" of Vivado.

Further clarification: I know how the lower bits of the address-lines are used to address single registers in AXI-Lite, but the Xilinx-Template doesn't seem to care about the higher bits, therefore my assumption that the addressing has to be done outside of the AXI-Lite block.

• Your question is not clear to me. You probably have a mental picture of the system which we do not share. As to "connected to a Zynq" I think you mean blocks of IP inside a Zynq like a processor, DRAM etc. Have you read the AXI spec from ARM? It talks about addresses and how to make an AXI infrastructure. It is not much different in principle from the old CPU bus but uses a awful lot more logic. – Oldfart Aug 22 '18 at 12:38
• @Oldfart: I have updated my question with a small diagram. The Zynq is not really relevant to the question, there just has to be 'something' on the other side of the bus which in my case is the "Zynq7-Procession-System"-IP-Block. – Blaubär Aug 22 '18 at 14:18

The address decoder is inside the interconnect. There are parameters at some level inside the IP block that set the addresses. Maybe they are not exposed at the top level as I think the top level file is generated, but they are in the heirarchy somewhere.

• Thanks. It turns out the source of axi_interconnect_v1_7 is actually not encrypted, and there it is, exactly like you said: parameter [C_MAX_M*C_NUM_RANGES*64-1:0] C_BASE_ADDR - not exposed to the user, but available in the verilog code. – Blaubär Aug 24 '18 at 13:13

The bus is physically routed to every block that needs access to it. Each block is responsible for decoding its own addresses, which is why each one has a "base address" setting. It's up to you to make sure that the address ranges don't overlap.

• This was my initial thought too, but if i look into the VHDL of a AXI-Lite interface as generated by "Tools->Create and Package new IP", the only existing generics are C_S_AXI_DATA_WIDTH and C_S_AXI_ADDR_WIDTH. Otherwise there are only input and output ports. So where does the BASE_ADDRESS come from? It is not hardcoded in the VHDL. – Blaubär Aug 22 '18 at 13:24

The reason is that AXI uses a handshake protocol (valid and ready) for each transfer. These are paired with every valid having one ready. (You can't give out many valids and wait for any ready to come back).