The Wikipedia page on silicon-germanium states that AMD and IBM worked on a 65nm SiGe process. Unfortunately the source is no longer up and I cannot find more information about the 65nm SiGe process.

I know that TSMC provides access to 90nm SiGe process. Does a 65nm SiGe process exist?

  • \$\begingroup\$ It must have existed... \$\endgroup\$ – Solar Mike Aug 23 '18 at 20:26
  • \$\begingroup\$ Because of the large investment in your project, it would probably be well worth directly contacting all of the major chip manufacturers you can, to inquire what processes they are capable of executing and current success rates. For a $30M customer they should at least be willing to tell you what the options are, relative costs and a relationship between success rate and die size and how that will affect your cost. There is a possibility even a not-yet-commercial process would be available to you, assuming you are willing to bear the costs currently preventing commercial use. \$\endgroup\$ – K H Aug 24 '18 at 0:19
  • \$\begingroup\$ @SolarMike I don't think the fact that AMD and IBM "worked on" a process implies that any devices were successfully built using that process. \$\endgroup\$ – Elliot Alderson Aug 24 '18 at 0:41
  • \$\begingroup\$ @ElliotAlderson “existed” does not mean it was manufactured in hundreds, thousands or millions... \$\endgroup\$ – Solar Mike Aug 24 '18 at 5:14
  • \$\begingroup\$ @SolarMike I don't understand your point. I said "any devices". It sounds like you are strongly agreeing with me... \$\endgroup\$ – Elliot Alderson Aug 24 '18 at 11:54

Does a commercially-available 65nm SiGe process exist? Sorta...

ST Microelectronics seems to have a 55nm BiCMOS process with a 320GHz ft device.

GlobalFoundries has a 90nm SiGe process with a 310GHz ft device.

I wasn't able to quickly find info on the TSMC process, but I would expect values in the same ballpark.

A bit of history, IBM spun out their foundry services and sold them to GlobalFoundries. The "selling point" of SiGe BJTs is that you can tack on a high performance NPN (and sometimes PNP) on to a high density CMOS process. The size refers to the CMOS process, and the actual NPN devices will be much larger.

| improve this answer | |
  • \$\begingroup\$ This implies that SiGe in the actual CMOS is probably coming soon. \$\endgroup\$ – The Photon Aug 23 '18 at 21:06
  • \$\begingroup\$ @ThePhoton Saw that, and considering that the article was from right around the GF acquisition, and GF now has a 7nm FinFET process, I'm guessing they didn't go that way. \$\endgroup\$ – W5VO Aug 23 '18 at 21:23
  • \$\begingroup\$ @W5VO: Do you have a sense of the size of the NPN devices? How many can fit in 1 mm^2? Is power draw a limitation when packing NPN devices densely? \$\endgroup\$ – Randomblue Aug 25 '18 at 10:01
  • \$\begingroup\$ So you need about 17 million gates to fit in a single reticle, and maybe keep the quiescent power below 7uW/gate? Seems unlikely, but I don't know for sure. There's a decent amount of research on SiGe ECL and CML that likely has more concrete numbers, but I don't have access to that right now. \$\endgroup\$ – W5VO Aug 25 '18 at 17:27

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.