Just to add to this question and @user55924 answer, because you mentioned parallel capacitance.
A capacitor can be modelled as follows:
where Rp is the lumped parasitic resistance and Lp is the lumped parasitic inductance. every capacitor has a special frequency point—a natural frequency: the impedance of the circuit is dominated by the capacitor at low frequencies, and is dominated by the inductor at high frequencies. The self-resonance frequency of a capacitor determines the frequency at which the capacitor switches from being mostly capacitive to mostly inductive effects.
Usually the capacitor is meant to have a low impedance to ground, putting a lot of capacitors in parallel can help reduce the impedance. It is important however to be vigilant of what capacitance values you are using.
As you can see in the figure above from "from Electromagnetic Compatibility Engineering, by Henry W. Ott, section 11.4.4."
Introducing multiple capacitance values in parallel, also allows for multiple anti-resonance peaks. And while at this peaks the impedance is lower, the dashed line consisting of four exactly the same parallel capacitors provides an overall better impedance.
Therefor when putting capacitors in parallel, try giving it a moment of thought if you want to put them in parallel to reduce the impedance, and if you will then use several capacitor of the same value, or capacitors of different values.
Also read: Antiresonance of multiple parallel decoupling capacitors: use same value or multiple values?