0
\$\begingroup\$

I am expecting a noise from a Power Source caused by motors.

However my setup already includes a buck-converter, and have the input and output capacitors. Should I add bypass capacitors for the powers on the IC's and Microcontroller like the Particle Photon. What will be its effect since it would add up capacitance values since they are all parallel.

\$\endgroup\$
  • 4
    \$\begingroup\$ Theory of bypass capacitors is not as simple as paralleled sums the capacitance, see EEVblog #859 - Bypass Capacitor Tutorial and EEVblog #1085 - Bypass Capacitors Visualised! \$\endgroup\$ – Jeroen3 Aug 24 '18 at 5:57
  • 4
    \$\begingroup\$ The rule I use is: "were possible use one capacitor per supply pin." This means a big/complex IC can have 10 or more capacitors. Some pins I use two: 100nF for HF and ~2u2 for LF. e.g. on-chip regulators. \$\endgroup\$ – Oldfart Aug 24 '18 at 6:26
6
\$\begingroup\$

The "Particle Photon" device already has bypass capacitors on it. In general, for any design you would want to decouple every IC.

At low frequencies you are correct, the capacitance adds up. But at higher frequencies, like harmonics generated from a buck converter, the bypass capacitors will act in a distributed way. An IC that has no bypass capacitor near it will have a higher (read worse) impedance to ground at higher frequencies. The "capacitor on every IC" rule of thumb makes it so that each individual IC sees their own nearby bypass capacitor first thing, so there will be a lower impedance to ground and better power-integrity for higher frequencies.

tl;dr: yes.

| improve this answer | |
\$\endgroup\$
  • 4
    \$\begingroup\$ each individual IC sees their own nearby bypass capacitor and to add to that: the fact that there is a capacitor nearby means that supply current spikes only need to travel in a short loop (remember that currents travel in loops). If the spike had to travel through the "far away" output capacitor of the buck converter, the loop would be much longer. That results in more supply ripple and more EM emissions (and potentially disturbing other devices in the area). \$\endgroup\$ – Bimpelrekkie Aug 24 '18 at 6:52
  • 3
    \$\begingroup\$ The rule for ICs is not actually one per IC, but rather one per power pin pair, located as physically close to it as possible. QFP/QFN ICs typically distribute these pairs around the perimeter, though for a BGA things get a bit more complicated. \$\endgroup\$ – Chris Stratton Aug 24 '18 at 14:33
2
\$\begingroup\$

Integrated Circuits will have 2--10nanoHenry inductance in each pin. Onchip capacitance from well-to-substrate reversed-bias junction is where the charge is supplied during those 50 picosecond logic-level transitions.

If you have 100pF onchip and 10nH pin inductance, that LC will ring with 150MHz frequency. That is 6 nanosecond sinusoid period, and 3nS to the first energy rebound zero crossing. Thus until 3nS (3,000 picoSeconds) passes, only the onchip silicon capacitances can provide charge.

Having a discrete Surface Mount cap right at the pin is the fastest way to re-supply the just-consumed charge.

| improve this answer | |
\$\endgroup\$
  • 2
    \$\begingroup\$ Specifically, one right next to each power/ground pin pair, which on ICs large enough for this to be an issue are generally placed next to each other and distributed around the perimeter. \$\endgroup\$ – Chris Stratton Aug 24 '18 at 14:34
  • 1
    \$\begingroup\$ @ Chris Stratton Yes. Having VDD/RTN be adjacent will reduce the loop area, reduce the inductance, reduce the needed stored energy, and thus allow faster recharging of the on-chip well-substrate and gate-bulk and drain-bulk capacitances (all 3 of which are the primary freely-available innately-included charge storage structure.) \$\endgroup\$ – analogsystemsrf Aug 24 '18 at 17:28
1
\$\begingroup\$

Just to add to this question and @user55924 answer, because you mentioned parallel capacitance.

A capacitor can be modelled as follows:

enter image description here

where Rp is the lumped parasitic resistance and Lp is the lumped parasitic inductance. every capacitor has a special frequency point—a natural frequency: the impedance of the circuit is dominated by the capacitor at low frequencies, and is dominated by the inductor at high frequencies. The self-resonance frequency of a capacitor determines the frequency at which the capacitor switches from being mostly capacitive to mostly inductive effects.

Usually the capacitor is meant to have a low impedance to ground, putting a lot of capacitors in parallel can help reduce the impedance. It is important however to be vigilant of what capacitance values you are using.

enter image description here

As you can see in the figure above from "from Electromagnetic Compatibility Engineering, by Henry W. Ott, section 11.4.4." Introducing multiple capacitance values in parallel, also allows for multiple anti-resonance peaks. And while at this peaks the impedance is lower, the dashed line consisting of four exactly the same parallel capacitors provides an overall better impedance.

Therefor when putting capacitors in parallel, try giving it a moment of thought if you want to put them in parallel to reduce the impedance, and if you will then use several capacitor of the same value, or capacitors of different values. Also read: Antiresonance of multiple parallel decoupling capacitors: use same value or multiple values?

| improve this answer | |
\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.