I recently read this report about the JPL x2000 avionics development project, which developed more modular avionics platform using commercial silicon, to cut cost and power. They opted for an architecture of two redundant protocols linking all electronics in the spacecraft. A high speed 1394 bus is used for large data, while an I2C bus (at 100khz) is used for low bandwidth controls. This is configured as a multi-master bus, where every node can communicate with every other.

I've not used I2C for more than single sensors, but from what I understand there are serious distance limitations. I within a spacecraft, there could be wiring harnesses of significant length.

In addition to having two redundant I2C busses, each device has a custom ASIC that provides isolation between the bus and the main chip pictured here  and here . Is this chip perhaps providing some kind of conditioning as well?

Can anyone explain why they might have chosen to use a protocol designed for communication within one PCB for communication within a large vehicle?

I know there probably isn't a single definite answer, but id be interested in hearing about what factors into that kind of choice.

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    \$\begingroup\$ Like you, I'm surprised by this choice. I've had hard time with long I2C buses myself: Memoirs of an overgrown I2C bus. \$\endgroup\$ Aug 25, 2018 at 17:32
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    \$\begingroup\$ It's all about capacitive loading and clock speed. There are many ways to extend the range of I2C, here is one app note that may help you: maximintegrated.com/en/app-notes/index.mvp/id/6208 The Nasa efforts reduced the clock speed to 100kHz, and I've seen successful long wire implementations as low as 10kHz. The biggest problem with low clock frequency is maintaining SMBUS compatibility if that is required. This may also help: nxp.com/docs/en/application-note/AN10658.pdf \$\endgroup\$ Aug 25, 2018 at 18:02
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    \$\begingroup\$ @Bruce In my experience, significant length for the I2C bus start at, say, 1 meter. This is where bus capacitance and interference pickup can start to become a problem. Capacitance and interference can be mitigated with buffers and shielding, of course. By the time one starts to consider multiple mitigations, one also starts to wonder "Why are we stretching I2C beyond its intended use? Why aren't we using a communication bus intended for our kind of range?" \$\endgroup\$ Sep 4, 2018 at 16:22
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    \$\begingroup\$ electronics.stackexchange.com/questions/106265/… "At 100 kHz, with a good error recovery protocol, 25m can be easily reached using basic wires. We were even able to reach 100m once with CAT5 cable" \$\endgroup\$ Sep 4, 2018 at 18:28
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    \$\begingroup\$ I've worked on aerospace hardware (PCB layout mostly), I'm surprised that I2C was chosen above RS-485, which has both better noise rejection and long wire-run support. I guess the multi-master aspect was a more important consideration. 485 does need more supporting components mind you. I2C is a royal PITA though, you won't catch me on a space rocket that uses I2C to run the coffee maker, let alone the important stuff :) \$\endgroup\$
    – user98663
    Oct 25, 2018 at 18:53

2 Answers 2


Yes, there is a length limitation with I2C but I think what they may be intending this for is to communicate with other ICs on the same board or boards located within the same subsystem rather than thinking about communicating with sensors deployed around the spacecraft and other spacecraft related systems. Most ICs today will incorporate I2C while data rates and distance can be seen as limitations, for onboard communication with other ICs it yields an extremely reliable method of data transfer and control. ICs such as power management functions (PMIC), onboard temperature sensors, MEMS-based accelerometers and gyros, to name just a few, I2C is a viable contender.

  • \$\begingroup\$ I had the same thoughts at first, but then I've looked more closely at the block diagram on p.5. One of the I2C buses [there's more than one on that block diagram] is running in parallel with the 1394 bus, \$\endgroup\$ Sep 24, 2018 at 20:36
  • \$\begingroup\$ They do have redundancy @NickAlexeev \$\endgroup\$ Sep 24, 2018 at 22:50
  • It was not designed to one PCB endpoint but rather many multidrop points over a short 400pF link max. Which might possibly up to 15m without buffers or repeaters using switches.
  • The I2C would be for short haul low bandwidth sensors (few m) and the IEEE 1394 high speed link for longer distance communication

Enhancements from report**

  • Both buses are multi- master and therefore support symmetric scalable and distributed architectures.
  • A layer of protocol is added to the I2C bus. This protocol includes a byte count after the address and two CRC bytes after the data. X2000 design also utilizes especial hardware messages commands to control critical functions. For these messages, command is sent followed by its complement to provide one more layer of protection.

  • Under catastrophic failure conditions such as bus power failure, both COTS bus sets may fail such that all communications among the nodes are lost. To re-establish the communication, each node can execute a distributed recovery procedure that consists of a sequence of link enable/disable activities.

  • since the cause of the catastrophic failure may not be within the avionics system, there is no guarantee that the distributed recovery procedure will succeed. Therefore, this approach is only the last recourse to save the spacecraft.


  • The last point means the Bus driver and cable. I am not surprised that the author did not mention any topics related to “Signal Integrity” such as space and system radiated EMI sand choice of cables or BER vs immiunity levels.
  • I think the report is flawed due to this suppression of information on signal integrity and error rates
  • all the report discusses is Digital layers above the physical layer 1 of the OSI 7 layers
  • However it does not mean they did not have the experts or the Analog data, it Was just not reported there.
  • They chose the I2C based on cost, availability of RAD hardened COTS and low power, so if they did manage the signal integrity issues well, they would not have to rely so much on robust fault-detection/correction/recovery redundant design.
  • There are mismatched termination methods that open collector drivers can use to enhance signal margin such as current source pull-up instead of passive R pull-up.


This is an area I supported Burroughs in mid ‘80’s in updating their Corporate Design Standards for EMC testing methods and of specifications for acceptance levels of immunity to conducted noise, radiated ESD, radiated burst RF, radiate plane waves for swept RF from 100kHz magnetic fields to x GHz radiated fields at very High field intensities using magnetic Coils with 1kW rack mounted Amplifier and dodecahedral flat antenna with opto feedback for servo E-field flat response to verify 0 bit errors in 10^10 bits.

NXP defines the attributes of this two wire standard called I2C as follows;

• Extremely low current consumption
• High noise immunity.
• Wide supply voltage range.
• Wide operating temperature range.

However it is limited by the cable capacitance and thus the choice and length of cable, level of nearby transient high currents or high slew rate voltage, the driver type active 50 ohm CMOS buffer type or current source termination and many variations.

The NXP spec says no problem for 100kHz up to 100pF load which may be typically 20pF/ft depending on impedance of the pair and then footnotes for handling 100pF to 400pF max for 100Kbps.

If it were me I would choose the highest impedance twisted pair (240~300+) then use constant current sink with latchup protection.

In any case an experience transmission line design engineer must design/ stress test and verify the signal integrity for these short haul links.


Students from Stanford Engineering developed enhancements for space communication that included Watch Dog Timers for power re-cycling and bit banging ports for recovery options multiplexed on the bus.


I would interpret that the main issues were not “signal integrity” on bit error rate but hard failures due to gamma radiation impulses that can induce latch-up in even large lithographic CMOS devices due to the high V/um field intensities of these high energy pulses. Their recovery methods from my experience were correctly implemented from my experiences with 25kV ESD in Project IDA in a MTS test home to a early ‘80’s


Project IDA was a Winnipeg Interdiscom Inc. R&D venture I participated in for a custom ISDN-broadband WAN with payTV, graphics weather data, opinion polling, digital telephony, fir/burgled alarms, meter reading, wired keyboard for high speed serial data and 2 inch arcs of ESD from vacuum tube TV static and fingers to our set top box in a dry winter!! It was the 1st large scale SCADA DS1 (1.544 Mbps) two way over RF to 100 homes in the world successfully tested and delivered. I was responsible for system test, and design and manufacturing of various BER test equip and overall 2 way network status ] monitoring and our team made it work. All of these 100 homes shared 1 coaxial cable and 2 RF for TDM DS1 tree/bus topology.

It was eventually sold to a company that owned Scientific Atlanta, Intellivision and a few others in Philadelphia.

  • \$\begingroup\$ I would guess that your 5th item in the Oppinion is the actual reason why NASA had proposed to use I2C this way. This choice raises doubt among the rest of us, because we don't know what types of COTS with what types of communication buses are available or not. \$\endgroup\$ Sep 24, 2018 at 23:10
  • \$\begingroup\$ @NickAlexeev Having supplied Honeywell with a lot of avionics motherboards, they are a major supplier but the author did not have to justify that plenty of COTS RAD hardened exist but like most things decisions end up being cost based with adequate reliability \$\endgroup\$ Sep 24, 2018 at 23:15

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