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74HC595 Datasheet here

I want to implement ac phase control on a lot of channels (20-25) using esp8266 module. Since it doesn't have as many GPIOs, I want to use serial to parallel shift register. Since phase control requires precise and fast switching (fast as compared to the ac line frequency), I want to evaluate whether shift register is even a good choice or not.

For this, I want to calculate the total time required to set a pin's output to either HIGH or LOW. MCU running at 80 MHz.

There is a timing diagram given in the datasheet:

timing diagram

timing table

I am having a difficulty relating these things together and with the clock frequency of the MCU. Any pointers on how to calculate will be really helpful.

Thanks

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  • \$\begingroup\$ It's neither the settling time nor the MCU clock you need to worry about, it's primarily the serial clock (often from an SPI engine in the MCU) and the number of bits. For demanding cases often a small FPGA is chosen for this task. \$\endgroup\$
    – Chris Stratton
    Aug 25, 2018 at 18:22
  • \$\begingroup\$ @chrisStratton - Assume my SPI clock frequency to be 1 MHz. How many clock cycles do I need to set my GPIO? \$\endgroup\$
    – Whiskeyjack
    Aug 25, 2018 at 18:46
  • \$\begingroup\$ @jsotola - SPI clock cycles. \$\endgroup\$
    – Whiskeyjack
    Aug 25, 2018 at 19:49
  • \$\begingroup\$ technically it is not SPI that you are using, only a serial clock and serial data on two pins ...... number of serial clock cycles required has nothing to do with the clock frequency .... the number of cycles is dependent on the number of bits that you are shifting out \$\endgroup\$
    – jsotola
    Aug 25, 2018 at 19:57

1 Answer 1

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To shift out 3 bytes with a 1MHz SPI clock would take 24usec. Say you have a 50 usec overall granularity in your timing including setup and clocking the data to the output.

That means your error could be as much as +/-25usec out of 1/120 second half cycle for 60Hz mains or about 0.3%. The error in terms of power will be different depending on where in the cycle the 'on' occurs, but it's not very much.

Seems feasible to me, maybe. You might well have trouble shifting that data out every 50usec without pauses because of other things going on the firmware (such as servicing the stack) but that's not directly relevant to your question. You'd probably have to set a high(est) priority timer interrupt and service it with your own bespoke ISR doing both the timing (counting down some registers and setting bits) and shifting out the data.

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