While reading some semiconductors datasheets, I've found something called "gate plateau". What do we mean by this term ?

AND8029 application note page 2, from ON Semiconductor written by Christoph Basso.


It's called a plateau because it's relatively flat, compared to the steep line before and after it.

It's caused by the Miller effect of the drain-gate capacitance holding the gate voltage relatively constant, despite charge being supplied to the gate by the gate driver.

In the first steeply rising below gate threshold region, the gate current is only charging the small inter-electrode capacitances.

At gate threshold, the Miller effect multiplies the DG capacitance by several orders of magnitude, reducing the rate of rise.

Once above the gate threshhold, the capacitance reverts to the inter-electrode capacitances, and the voltage rises steeply again.

  • \$\begingroup\$ So this effect happens at the threshold voltage which makes a MOSFET fully ON (Rds minimum and Ids Maximum) \$\endgroup\$ – luxina pado Aug 27 '18 at 20:03
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    \$\begingroup\$ No, this effect happens at the threshold voltage that makes the FET partially on, and in the active amplifying linear region. The Miller effect only happens when the device is in the linear region. It's necessary to increase the gate voltage well beyond the plateau voltage to get the minimum Rds. \$\endgroup\$ – Neil_UK Aug 28 '18 at 4:16

Gate plateau voltage is where the V(gate) changes very little because, at that moment, the charge demanded into C_gate_drain is huge.


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