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I want to be sure, with arbitrary precision (let say, for example, with 10^-100 certainty), that I can check the following statement (in binary):

x = 49

That is, I want to check that a number that is (correctly) coded in a binary electrical signal is the same as a second number (also correctly coded in binary).

I'm a novice at electrical circuits, but I've worked out that I can perform this operation using 6 exNors and 5 And gates. I'm assuming there is some small uncertainty in these logic gates, and that there's a super small chance that these gates can misfire (maybe even so small it's associated with the quantum electrical noise).

If I wanted to make this system have arbitary precision, what could I do to prevent these errors from /ever/ occuring?

One option I thought of is to perform the same operation multiple times and AND-gate the results together. (I am perfectly fine losing "efficiency," that is, I don't mind if the circuit has "false negatives" where the number is correct but since there was a misfire in one of the circuits it does not return a 1.)

Is there a way that I can analyze the probabilities of the circuit being correct? And what types of electronics would be ideal for this type of system (my guess would be that higher voltages would have less fundamental noise, so they would be the best to construct the system.) It seems as though there is some work on simulating the propagation of these errors using some advance techniques like monte-carlo simulations and baysian analysis. But is it not possible to get a crude, order-of-magnitude estimate for the amount of uncertainty/error per gate?


*Moved information in comments to the question where it belongs*
The purpose of this device I think is outside the scope of electrical engineering, but it's sort of related to metrology and quantum mechanics. I agree it's a very unconventional thing to be concerned with. I am first trying to get some kind of grounding on the topic because of how unusual it is. Any implementation (or discussion of errors, no matter how small) would be helpful (not concerned with hardware, frequencies, as long as it's digital).

Maybe rephrasing the question. If I performed this comparison operation on a microcontroller over and over, how much time (or how many repetitions) would it take until it misfired and gave an incorrect comparison? (Minutes? Days? Millennia?) And does this error loosely scale linearly/polynomially with the number of gates? So, for example, if I have 600exNors now instead of 6, does my operation misfire 100 times faster? (implying the errors scale linearly)

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closed as unclear what you're asking by Chris Stratton, winny, Harry Svensson, Maple, RoyC Aug 30 '18 at 7:30

Please clarify your specific problem or add additional details to highlight exactly what you need. As it's currently written, it’s hard to tell exactly what you're asking. See the How to Ask page for help clarifying this question. If this question can be reworded to fit the rules in the help center, please edit the question.

  • \$\begingroup\$ I understand this is a fairly unconventional question, but downvotes should always be accompanied with comments/feedback. \$\endgroup\$ – Steven Sagona Aug 28 '18 at 1:24
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    \$\begingroup\$ Are you concerned about data corruption? \$\endgroup\$ – Daniel Aug 28 '18 at 1:30
  • \$\begingroup\$ Alright, so I believe we're talking about transistors on a silicon wafer and how going smaller introduces more quantum noise (through quantum tunneling). We're at what, 7 nm now. - If this is indeed what you're talking about then update your question with that information. - If this is the essence of your question, then perhaps it's time to clean it up at the same time. - FYI, we are not using 5 nm transistors yet. We are using 7 nm transistors where this problem does not exist (AFAIK). \$\endgroup\$ – Harry Svensson Aug 28 '18 at 2:22
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    \$\begingroup\$ You might want to add some context - why are you concerned about this? The closest thing that comes to mind for me is single event upsets, caused by high energy particles (radiation). This is a significant problem for spacecraft. However, it's really not a problem on Earth (although I can't put any numbers on the probability of a bit flip in discrete logic chips, my guess is its effectively never). Also, how your circuit works is obviously relevant - if it's purely combinatorial (no clocks or memory), a single error doesn't really make sense, because the circuit is constantly refreshed. \$\endgroup\$ – Selvek Aug 28 '18 at 2:53
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    \$\begingroup\$ @StevenSagona, since you mentioned quantum mechanics, remember there's always a nonzero probability that a tennis ball will quantum-tunnel through a brick wall. If you want to consider events of that kind of probability, you can never guarantee your circuit won't produce a wrong output, or even just quantum-teleport somewhere you can't measure the output at all. \$\endgroup\$ – The Photon Aug 28 '18 at 3:14
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I'm a novice at electrical circuits, but I've worked out that I can perform this operation using 6 exNors and 5 And gates.

Yes you can (if 6 is the number of bits you want).

I'm assuming there is some small uncertainty in these logic gates, and that there's a super small chance that these gates can misfire (maybe even so small it's associated with the quantum electrical noise).

The chance is negligible, by which I mean, it doesn't happen. You may as well ask whether there's some small uncertainty in a tennis ball's position, so that there's a super small chance that it will teleport across the room (maybe even so small it's associated with quantum noise). Or the probability that every now and then, your car will go backwards for a moment when you press on the accelerator, because of quantum noise.

If I wanted to make this system have arbitary precision, what could I do to prevent these errors from /ever/ occuring?

You can't, there's always the possibility that your entire apparatus will quantum-tunnel into the middle of the Milky Way never to be seen again.

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    \$\begingroup\$ I've been pondering a suspicion that as long as a gate is given it's inputs long enough to propagate, it seems like so many electrons are involved that if the output is not 100% accurate it has to be because the gate is broken. \$\endgroup\$ – K H Aug 28 '18 at 4:02
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Bit Error Rate BER can be predicted for different types that affects margin to error. Errors can injected by a measured amplitude of energy required to cross the binary logic threshold . A driver has a defined source impedance and connections have a characteristic impedance and bandwidth as well as the input has a bandwidth limit.

It can also be controlled by design of supply voltages and thresholds as well as filtered in time , when it is synchronously latched into memory.

Since 10e100 is a really big number of operations, to measure this many cycles is very impractical.

A test can be designed with confidence level of achieving a certain error rate with a combination of stress tests for low supply voltage, high temperature, vibration with radiated and conducted noise including ESD and power-line transients.

Noise effects from all sources including gamma rays can be reduced by redundancy, but the cost of verifying extreme levels of low error rates must be supported with a healthy budget, great design specs including; the expected operating environment and diligent design verification test DVT methods.

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Assuming this is not about Quantum Mechanics.. or tennis balls and walls even... and, simply about dealing with "stuck bits" or other hard failures on the IC and how to protect against computing failures if that occurs....

You could always use Triple-Mode Redundancy (TMR) for the design. This is a technique that is used in "high-upset" environments such as space (radiation effects) to reduce probability of a failure when an upset occurs. It votes 3 outputs to determine the correct value. You can do this by design, or let (some) tools do it for you at synthesis. If concerned about radiation, there are Rad-Hard processes Honeywell offers at their foundry.

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