I'm unable to figure out how to implement an ADPLL on an FPGA that can take in an arbitrary periodic input and lock onto its frequency (some finite range is okay) and phase. A square wave output will do.
As a first step I thought of assuming that the input is a sine wave. I know how to digitise the same using the onboard ADC. How do I proceed from here?
Any links to existing code repositories that implement all or parts of this are welcome.