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This is part of the pulse output circuit for cable fault location, but the pulse signal output to the cable is suppressed. I guess the reason for the impedance mismatch, but how can we achieve the match? Is it a series or parallel connection of a resistor directly at the output?enter image description here

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  • \$\begingroup\$ You might want to post expected and measured waveforms, cable impedance, and any other details of the application that could be relevant--for example, are you looking for shorts, opens, or both? \$\endgroup\$ – Cristobol Polychronopolis Aug 29 '18 at 12:59
  • \$\begingroup\$ Note the IRF840 is being driven from 0-5v. Datasheet says 40A at 5vgate, but if Vg drops to even 4.5v, this will drastically reduce the drive capability. My opinion, it would work much better with +/-10vg and a dedicated gate driver IC. \$\endgroup\$ – rdtsc Aug 29 '18 at 13:15
  • \$\begingroup\$ I understand that part of the circuit is designed to quickly drive the gate of Q405. But I do not understand the logic behind the rest of the circuit, the 10k resistors and the 1uF capacitor will make it respond slowly except for the case where Q405 is switched on. If you wanted impedance matching (to the cable) then this is not the way to do that. This circuit cannot generate a proper pulse. Also be clear where the circuit comes from, did you design it? Is it proven to work? \$\endgroup\$ – Bimpelrekkie Aug 29 '18 at 13:20
  • \$\begingroup\$ This is a circuit that uses a time domain reflectometer that locates the fault location of the cable, using an FPGA chip. \$\endgroup\$ – yongleili Aug 30 '18 at 1:12
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That circuit is very assymetric between its low-going and high-going impedance. Adding just a resistor somewhere will not "impedance match" it to any cable.

This circuit is intended to test the cable with a single edge, not a pulse. The only thing drawing the output high is R406. At 10 kΩ, that's way more than the impedance of any cable you will find.

Everything is intended to stabilize, then the circuit is triggered to cause a falling edge. Since that edge is AC coupled, and R407 keeps the cable at 0 V in steady state, the edge will actually be negative on the cable. The propagation and reflections of this single edge are then measured.

D408 clamps the amplitude of the falling edge on the cable. Perhaps this is to provide a more known pulse amplitude.

Since everything that is measured will occur between the outgoing pulse edge and any returning reflection from the far end of the cable, there is no need to terminate at the sending end. The driver is essentially 0 impedance. That means anything reflected back to the driver will be reflected back again onto the cable with negative amplitude. Presumably, the measuring circuit takes that into account.

If you really want to absorb returning reflections, you can add a resistor in series with the cable. However, now you have to know the characteristic impedance of the cable.

Or

Or, this is just a badly designed circuit. You didn't say where this device came from, so maybe it's just not a competent circuit. There is some significant evidence of this:

  1. The way the two BJTs are driven is highly dependent on the 5.3V supply voltage.

  2. The BJT gate drive seems to go to some trouble to have fast edges both ways. However, even with the FET turning off instantly, the 10 kΩ pullup will make the rising edge very slow.

  3. RDTSC points out in a comment that this FET is not intended for only 5 V gate drive. That is a really big hint at gross incompetence.

  4. Limiting the pulse amplitude to a diode drop doesn't make much sense. The signal to noise ratio would be higher with a higher amplitude, like 5 V, without causing any other trouble.

You didn't say where this circuit came from. I originally took it at face value and assumed this was the circuit in some tester you were using. Given the many indications of bad design, this must be a jig in your lab someone who didn't really know what they were doing cooked up. In that case, the correct solution is to go back to whatever problem it was originally trying to solve, and design a proper circuit to solve it.

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  • \$\begingroup\$ This is a circuit that uses a time domain reflectometer that locates the fault location of the cable, using an FPGA chip. I simulated with TINA and found that the edge of the output signal is particularly slow. \$\endgroup\$ – yongleili Aug 30 '18 at 1:13
  • \$\begingroup\$ This device can be tested for cable failure, it should be used a single edge.But I looked up the time domain reflectometry data for cable fault measurements and found that they used the pulse method. Moreover, the output pulse of this circuit is suppressed by the cable, and the maximum power output cannot be achieved. \$\endgroup\$ – yongleili Aug 30 '18 at 1:26
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You don't mention the cable impedance, but if it's less than 10K the rising edge of the pulse is going to be pretty slow. If it's a low-going step and you don't care about the rise time, I don't see an issue. If you want a fast pulse, however, you should use a push-pull driver.

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  • \$\begingroup\$ This is a circuit that uses a time domain reflectometer that locates the fault location of the cable, using an FPGA chip.If the 5V pulse is directly output, it will decay quickly in the cable, so a higher pulse amplitude is required. \$\endgroup\$ – yongleili Aug 30 '18 at 1:11

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