The code snippet below shows a two-step variable manipulation:
1) Convert an integer to an unsigned number
2) Cast an unsigned number to a std_logic_vector and extract a certain number of uppermost bits.
Could these two steps be consolidated into a single one? That is, is this just typecasting (wire connections) or is some sort of clocked circuitry involved that could potentially result in a problem?
signal integrator_inter_uns : unsigned(20 downto 0):= (others => '0'); ... ... counter : process(CLK) begin if clk'event and clk = '1' then -- oveflow if pwm_counter = N then pwm_counter <= 0; -- 1 elsif pwm_counter = 1 then pwm_counter <= pwm_counter + 1; integrator_inter_uns <= to_unsigned(integrator, integrator_inter_uns'length); -- 20 bit unsigned -- 2 elsif pwm_counter = 2 then pwm_counter <= pwm_counter + 1; data <= std_logic_vector(integrator_inter_uns(15 downto 0)); -- 3 elsif pwm_counter = 3 then pwm_counter <= pwm_counter + 1; dac_input <= data; else pwm_counter <= pwm_counter + 1; end if; end if; end process;