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I'm curious as to the physical reason as to why the effect of channel length modulation in an N-MOS actually increases when the Vgs voltage is increased?

See the plot below: enter image description here

For a long channel device, as the Vg is increased, the R0 is actually decreasing. This makes sense if you think about channel length modulation as the inverse of the slope of the Ids-Vds in the saturation region, and that all of these slopes have to intersect at the early voltage.

But physically why does this occur?

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Stated simply, higher gate voltage means more electrons in the channel. That means more current can flow between drain and source; thus lower resistance.

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  • \$\begingroup\$ Excellent answer. Very straight forward \$\endgroup\$ – KingDuken Aug 30 '18 at 0:03
  • \$\begingroup\$ I guess it is that simple \$\endgroup\$ – Michael E Aug 30 '18 at 0:29

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