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I have an LVDS ADC connecting to an Altera Cyclone IV FPGA. The data pins come in 7 differential pair channels, for a total of 14 pins.

Although each differential pair is physically 2 pins, my Verilog code expects only one signal for each pair.

How should I tell the FPGA that each differential pair should be merged into one signal for my Verilog code? Is this done in Verilog? Is this done in the contraints file?

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The Cyclone FPGA has differential line receivers built-in, and you use those by instantiating them in your design. My usual approach is to create a separate module that represents the "pad ring" for the chip, and instantiate them there. You'll have two external pins for each logical signal used in the interior.

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Altera FPGAs can easily interface LVDS signals. Assign a signal to a pin in Pin Planner, then select that pin type as LVDS and a complementary pair will be generated automatically. Plus it will also assign a negative pin when You select location of positive pin and vice versa.

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