I have an LVDS ADC connecting to an Altera Cyclone IV FPGA. The data pins come in 7 differential pair channels, for a total of 14 pins.
Although each differential pair is physically 2 pins, my Verilog code expects only one signal for each pair.
How should I tell the FPGA that each differential pair should be merged into one signal for my Verilog code? Is this done in Verilog? Is this done in the contraints file?