I am reading the product page for TSMC's 20nm process. It states

Compared to its 28nm node, the 20nm process provides 15% better performance and can reduce total power consumption by a third.

What exactly is meant by "performance" in this context? Which metric(s) is improved by 15%?


A very important (maybe even the most important) parameter of CMOS processes is the number of gates per area. I think that this 15% better performance is directly this number as it is easy to use for translation to a business case (does it make sense to use 20 nm instead of 28 nm?).

This number (often expressed in \$kgates/mm^2\$, where 1 kgates is 1000 gates) can be directly related to processing power. For example to make a certain design CPU the company using or owning the design will know how many (k)gates are needed.

From that they can calculate how much area is needed for a certain function. Since in chip manufacturing Area is hard coupled to price (prices are calculated in \$$$/mm^2\$) that would give a good indication of cost as well.

Since most modern CMOS processes offer high performance (but power hungry) and low power (but less performance) versions of the same process, using the actual maximum speed of a process as a performance indicator is more complex than the number of gates per area parameter.

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  • \$\begingroup\$ Are you saying performance and gate density are synonyms in this context? Why not use the more precise terminology "gate density"? \$\endgroup\$ – Randomblue Aug 30 '18 at 8:10
  • \$\begingroup\$ @Randomblue because marketing teams like to just say 'we are this much better' to give it a number. In reality, comparing technologies is very complex and takes a lot of time to do, and what technology performs better depends heavily on how you measure things (eg, 'power reduced by a third': digital or analog? if digital: static or dynamic? or is it some ratio of static vs dynamic? ) \$\endgroup\$ – Joren Vaes Aug 30 '18 at 8:13
  • \$\begingroup\$ No these are not the same, see my last paragraph, the low power version of a 20 nm process has the same gate density as the high performance version but lower speed. So I think "performance" should also include the "operations per unit of power". \$\endgroup\$ – Bimpelrekkie Aug 30 '18 at 8:14
  • \$\begingroup\$ Actually the true measure of technology node performance is the actual silicon area per a sizable IP block, something like video encoder or something, not just transistor density. The translation into business-important silicon area isn't easy, because each competing technology have distinctive architecture of qualified libraries, different compiling and DRC rules, and smaller process might require more "gray transistors" to ever function. I have seen very surprising results. \$\endgroup\$ – Ale..chenski Sep 12 '18 at 16:21
  • \$\begingroup\$ @Ale..chenski I never mentioned transistor density, I mentioned gate density which is different. Although you're right that a fair comparison can only be made using a certain IP block (also: which one, there are many designs), this is never done as it is impractical. To use your measure (and use an IP block) that design would have to be actually synthesized to know the actual size. And synthesize it for each technology you want to compare. That's a lot of work. kgates/square mm or RAM, ROM, Flash density etc. is much easier (requires less effort) to compare. \$\endgroup\$ – Bimpelrekkie Sep 12 '18 at 16:26

Speed. Smaller geometry processes are usually faster. Smaller gate lengths and parasitic capacitances give higher speeds. The smaller gate has a lower resistance and so can drive the next gate faster. Much of speed is about the balance of resistance and capacitance smaller geometry transistors gain twice from this. By speed I am referring to the propagation delay through a layer of logic which in turn leads to maximum clock speeds.

Lower power consumption as mentioned, capacitances and therefore charge transfer (currents) are lower.

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    \$\begingroup\$ Speed is a very broad term, and might not really be helping the OP that much (you just replaced 'more performance' with 'more speed/faster'). What speed? fT? fMax? Maximum stable gain frequency? \$\endgroup\$ – Joren Vaes Aug 30 '18 at 8:07
  • \$\begingroup\$ Answer edited to address this for the broader community. I would expect an OP of that reputation to understand what speed means in the context of a CMOS process. \$\endgroup\$ – RoyC Aug 30 '18 at 8:13
  • \$\begingroup\$ Yes but this is "performance" in the marketing sense, not engineering sense (as that is too complex to put in a marketing blurb). \$\endgroup\$ – Bimpelrekkie Aug 30 '18 at 8:17
  • \$\begingroup\$ @Bimpelrekkie I cant disagree with that. However having read the blurb my reading is that this is what they are referring too. \$\endgroup\$ – RoyC Aug 31 '18 at 16:22
  • \$\begingroup\$ "The smaller gate has a lower resistance and so can drive the next gate faster." - usually it is quite opposite - smaller gates have higher resistance and less drive strength. And traces are narrower, with higher resistance. However, smaller gate has less capacitance, and threshold voltage gets smaller, less delta-V to switch, so the interconnect delay might end up even, and the gain is only in gate prop delay. That's why there is no "twice" and only 15%. \$\endgroup\$ – Ale..chenski Sep 12 '18 at 16:01

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