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I'm designing a circuit that will disconnect a connection when 5 consecutive square wave pulses are missing. If less than 5 consecutive pulses are missing then I want to reset the counting process.

      _   _   _   _  1  2  3  4  5      _   _  1 2 3 4 _   _
In  _| |_| |_| |_| |___________________| |_| |________| |_| |_

                                   ____
Out ______________________________|    |______________________

To give an idea:

I'm thinking of using a counter that will count the number of pulses. This will connect to a multiplexer, to initiate selection between counter reset or charge bank of cap(s). Bank of capacitors charge to reach 5V. This will be compared(op-amp) to ~4.9V.

The capacitors will initiate charge after each pulse, but will discharge and start charging when the counter resets. If 5 consecutive pulses are missed, the caps will be at 5V. This 5V will be higher than 4.9V at the comparator. Which will create the signal I need....(the rest of the circuit I have already).

So I need some ideas from the experts. Do you guys think this is a good approach? Do you have a better way of doing this?

Edit: Counter will be used to count missing pulses. The time interval will always be the same and very robust. Duty cycle is going to be 30% on and 70% off. I will have to pick the correct capacitors but it is not critical now. Frequency is 10Hz

Any feedback is appreciated.

Thanks in advance.

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    \$\begingroup\$ I've added a timing diagram for you to edit. A good one is much better than a bunch of words. Note that I've assumed the output will go high in the absence of pulses. What use will your counter be for counting missing pulses? What frequency are your pulses? Are they always the same time interval? What about duty cycle (on / off ratio)? \$\endgroup\$ – Transistor Aug 30 '18 at 20:07
  • \$\begingroup\$ You are right. Images and diagrams speak thousand words. I'm just in a pinch. Thanks for adding the image. Yes, counter will be used to count missing pulses. The time interval will always be the same and very robust. Duty cycle is going to be 30% on and 70% off. I will have to pick the correct capacitors but it is not critical now. Frequency is 10Hz \$\endgroup\$ – Fugy Aug 30 '18 at 20:17
  • \$\begingroup\$ Don't forget to edit your question to include the details requested in my comment. \$\endgroup\$ – Transistor Aug 30 '18 at 20:19
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    \$\begingroup\$ Perhaps a re-triggerable monostable would be a useful single-chip solution to generate a reset after an idle-clock period, especially if clock period is fixed. \$\endgroup\$ – glen_geek Aug 30 '18 at 20:27
  • \$\begingroup\$ "Yes, counter will be used to count missing pulses." Again, how can you count missing pulses? Do you mean a timer? \$\endgroup\$ – Transistor Aug 30 '18 at 21:05
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schematic

simulate this circuit – Schematic created using CircuitLab

Figure 1. A simple pulse extender.

How it works:

  • When IN goes high BUF1 output goes high. C1 is charged through D1. BUF2 turns on.
  • When BUF1 goes low C1 starts discharging through R1.
  • If VC1 drops to about 1/3 of supply voltage then BUF2 will turn off. The time taken for this is approximately \$ \tau = RC \$. You want a 5 x 0.1 s = 0.5 s delay. With a 10 µF capacitor you can calculate \$ R = \frac {\tau}{C} = \frac {0.5}{10^{-5}} = 50\ \text k\Omega \$.
  • Meanwhile, if another pulse comes within 500 ms the circuit is reset.

Use Schmitt trigger gates for the buffers. If you are using inverting gates then reverse D1.

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