# How to read multiple Verilog files in Design Compiler?

I'm trying to read multiple Verilog files in Design Compiler, but I have found just one command, read_verilog. It can read only one file at a time.

If I've got 1000 Verilog files, do I have to use 1000 read_verilog commands?

• Make a loop and iterate though a list? – Dmitry Grigoryev Sep 7 '18 at 12:19
• @DmitryGrigoryev As a user of Design Compiler, the question doesn't seem unclear to me, however phrasing is not ideal. – ahmedus Oct 5 '18 at 22:10
• @ahmedus OK, perhaps I was too quick to VTC. Glad that you had the time to answer. – Dmitry Grigoryev Oct 6 '18 at 18:06

In your installation directory you should have a document named something like "dcug.pdf" (Design Compiler User's Guide). The one I found online (dcug_2016.pdf) has an example 10-3, on page 10-14, that shows an example script of reading in multiple files.

• Would you mind let me know how to make a listofFiles ? – greeting Sep 4 '18 at 12:24
• My answer was wrong, so I updated it. You should also be able to type "read_verilog --help" (probably from within DC shell) and see how it works. there should be a command line reference in the docs directory too. Good luck. – CapnJJ Sep 4 '18 at 13:50

The read_file command has more options than the read_verilog command and it provides a solution for your need. You can specify directories instead of single files.

The following command reads all Verilog files in the specified directories.

read_file {./module1/rtl ./module2/rtl} -autoread -format verilog -top MyTopModule


The -autoread option is required for the files to be compiled in the correct order. In addition, the top module of the design is specified.

If there are too many directories, the -recursive option saves lives.

read_file {./} -autoread -recursive -format verilog -top MyTopModule