# Sequence Detector with multiple inputs

The question:

Design an automaton that receives inputs X0, X1 and produces outputs Z0, Z1.

• Z0 is 1 If the last two bits of X0 are the complement of the last two received on X1.

• Z1 is 1 If in the last two bits of X0 and X1 there is an even number of 1

Example:

X0 0 0 1 1 0 0 1 1 0
X1 0 1 0 0 1 1 1 1 0
Z0 - 0 1 1 1 1 0 0 0
Z1 - 0 1 1 1 1 0 1 1


I have problem to solve this type of question. I'm tried many times to solve this type of problem but I couldn't. This is not homework, it's a question from my last exam.

• Your illustration does not seem to be correct. The last two X0s on the right are 0 and 1, an odd number of 1s, but Z1 is 1. The beginning of the sequence has X0 as 0 0, but Z1 is 0. Neither of these corresponds to your stated rule. Sep 1, 2018 at 11:52
• You should show us what you have tried. Can you describe in words what you need to design? Sep 1, 2018 at 12:18
• @WhatRoughBeast: The example is correct. "Last two inputs" really means "current and previous inputs". Sep 1, 2018 at 12:51
• @DaveTweed , Thank you fro approving that it is correct as you said the previous and current. Could you please help with the question? I'm searching for this type of question with solution to learn how to solve, but nothing. Sep 1, 2018 at 13:02

This isn't really a sequence detection problem. All you need to do is remember the previous state of each input (two DFFs). The rest is combinatorial logic on those bits combined with the current value of each input (four 2-input gates).

Solution:

Explanation:

Note that A is high if the current inputs are different, and B is high if the previous inputs are different. Therefore, a simple AND gate provides the Z0 output if both of those are high.

But note that A also indicates whether there's an odd number of ones in the current inputs, and B also indicates whether there's an odd number of ones in the previous inputs. If both of these are high, or both of them are low, then there's an even number of ones in the current and previous inputs. One additional XNOR gate provides the Z1 output.

• Thank you for your comment. In my university it's called State automata / Analysis of synchronous sequential circuits (just traslated). If you can help me it would be nice Sep 1, 2018 at 13:14
• The answer above IS help. You need to take my hints and try to come up with a solution. Lets us know if and how you get stuck. Show us your work by editing it into the question. Start by drawing a truth table for the combinatorial logic. Sep 1, 2018 at 13:17
• Sorry but how should I start? you saying that it is two D FF but how should I understand it why two D FF? D FF works in way of what D is so the next state will be D ignoring the current state,yes? Thank you. Sep 1, 2018 at 13:32
• Yes. But it sounds like this kind of problem is way beyond your current level of understanding. You say you got this question in a university exam. If you were this lost in the course material, you should have asked for help long before you got to the exam. I'm going to go ahead and show a solution (but hidden in case others want to try to work it out for themselves first). Sep 1, 2018 at 13:47
• Thank you so much for your time. I'm a bit starting to get the thing,I have some questions: 1)The Prev state,if you have nothing in the Prev what is written, I mean it's the first input 1 and 0 what it gives on the D FF? 2)There are some good source to learn such things? 3)The question requested to design an automata of this? is there some tricks to draw the automata? because mostly it's only 1 input Sep 1, 2018 at 14:24