I began to read up on transistors, which led me to this post on electronics stackexchange.

At the end of the original post, the question asks "the voltage at the base would be a sine wave with the DC bias as the baseline, correct?"

I understand the V2 with the two resistors in series is a voltage divider.

I am struggling to see how at the node connected to the base, the voltage is going to be simply the sum of V1 and V2, resulting in the AC signal superimposed on the DC signal from V2.

I think I can best express my confusion in the form of the second image below.

The voltage between the capacitor and GND is ground no matter the input oscillating voltage before the capacitor.

Then why should the first case be the sum of the AC from source 1 and DC from source 2 ?

enter image description here

enter image description here


Also, I remember playing with small batteries as a child. When I put hooked up those batteries of the same voltage in parallel, the voltage output was the same as having a single battery, which I believe is kind of like the first case. (So why should it be the sum of the two voltage sources in the case of the first image?)


In the first circuit, if properly chosen, C1 will charge to the average voltage difference between the base and V1. If V1 is average zero, it will charge to 0.5V. The time constant will be 50 ohms * C.

The Thevenin equivalent of the resistors and 1V source is a 0.5VDC source with 50 ohms in series. If the impedance of C1 at the frequency of V1 is much lower than the 50 ohms, then most of the voltage appears at the base.

We know Xc = 1/(2*pifC) so C >> 1/(2*pi*1kHz*50) = 3uF. So suppose C is 30uF, then the time constant to charge will be 1.5msec and after 10msec or so it will be almost fully charged.

Here's a simulation with the AC voltage at 100mV peak and C1 = 30uF (and ignoring the base impedance):

enter image description here

When the voltage sources are first applied, the capacitor is assumed charged to zero volts, and it takes some time to charge to close to the final voltage.

  • \$\begingroup\$ Thank you so much for the response. What if V1 was a DC voltage source with + toward the base? Also what if instead of C1, you have a resistor? I think for the first case, C1 gets charged jusy enough to give you the node voltage the same as the voltage division of V2 due to the series resistors. In the second case, if you have a resistor instead, im not sure what happens. \$\endgroup\$ – Blackwidow Sep 4 '18 at 3:23
  • \$\begingroup\$ It would start out at 1V and exponentially decay to 0.5V with the time constant C1*50\$\Omega\$, similar to the above but going down and without the 1kHz sine. Assuming the cap was not charged to begin with. If you have a resistor R1 instead of C1 you have a simple 3 resistor voltage divider and the base voltage is (V1/R1 + V2/100)* (50*R1)/(50+R1). \$\endgroup\$ – Spehro Pefhany Sep 4 '18 at 3:43
  • \$\begingroup\$ my apologies. Could you give me a hint on how you got (V1/R1 + V2/100)*(50*R1)/(50+R1) = v1*(50/(50+R1)) + v2*(R1/(100+2R1)) ? I see that i have three voltage dividers but not sure how to do the math... \$\endgroup\$ – Blackwidow Sep 4 '18 at 4:12
  • \$\begingroup\$ Sorry again, i think i figured it out. (Superposition due to linearity) \$\endgroup\$ – Blackwidow Sep 4 '18 at 4:20
  • \$\begingroup\$ Yup, you got it. In general if you have n resistors connected together with a voltage source (could be 0V = ground) on each, the voltage at the junction is (V1/R1 + V2/R2 + ..+ Vn/Rn)*(R1||R2||..||Rn). \$\endgroup\$ – Spehro Pefhany Sep 4 '18 at 11:44

Your second schematic bears no relation to the first. The voltage at the nexus of the two resistors and one capacitor will be the sum of the voltages at the other ends of those components in inverse proportion to their impedances.

In other words, the two resistors and one capacitor form a three-way impedance divider (ignoring the transistor for now) which is like a resistive divider except that the "resistance" depends on frequency. You can think of an ideal capacitor as a resistor that has infinite resistance at DC and decreasing impedance as frequency increases. So we have three inputs:

  • 0V (ground) via 100R
  • 1V (V2) via 100R
  • a 1kHz sine wave via some capacitance C1

If we disconnect the sine wave source, we have a simple resistance divider, and since we have equal resistors, the output of the divider will be 0.5V. The value of the capacitor is not given, but if it's 2.2uF, then it will also be about 100R at 1kHz, in which case the output of the impedance divider will be the average of the three inputs. At lower frequencies, the impedance of the capacitor is higher, and so V1 will have less impact on the output of the divider. At higher frequencies, the impedance of the capacitor is lower, and thus V1 will have a larger impact on the resulting voltage.

All of that said, we've been ignoring the transistor in the circuit. The base-emitter junction of a transistor acts something like a diode with a nonlinear relationship between current and voltage, so where the voltage at the output of the impedance divider would increase, this is tempered by the fact that current will be driven into the base of the transistor. Likewise, where the voltage would decrease, less current is driven into the transistor base. This affects the actual voltage at the node where the two resistors, capacitor, and transistor base all meet up, but the details depend somewhat on how the other two terminals of the transistor are connected.


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