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My professor presented the NOT gate in the Transistor-Transistor logic as the following:

enter image description here

Where V is always 5Volts. The two symbols are MOSFETs N-type transistors. The first transistor (which is always conducting) is called the Load transistor, and the second is the one who really does the logic operations. (By first I mean the top one, and second the bottom one).

What I'm unable to understand is why does this Load transistor exists. Can't we just plug the Drain of the other transistor directly in V? Why do we have to add a transistor between them?

Thanks in advance.

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    \$\begingroup\$ "Can't we just plug the Drain of the other transistor directly in V", then where would the output be? \$\endgroup\$ – Harry Svensson Sep 4 '18 at 13:12
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    \$\begingroup\$ This is not transistor-transistor logic (TTL), it is depletion load NMOS logic. \$\endgroup\$ – Elliot Alderson Sep 4 '18 at 13:21
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    \$\begingroup\$ I also question why some professors still talk about obsolete logic types like this. I mean, depletion transistors, for logic, no-one uses that anymore. It is not like CMOS is difficult to understand. \$\endgroup\$ – Bimpelrekkie Sep 4 '18 at 13:32
  • \$\begingroup\$ Bimpelrekkie, we had a brief tour in the old logic types (like this one) before studying CMOS logic properly. \$\endgroup\$ – Vitor C Goergen Sep 4 '18 at 17:17
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Compare these two circuits:

schematic

simulate this circuit – Schematic created using CircuitLab

In which one(s) do you think the meters VM1 and VM2 can be made to show a voltage other than V = 0 Volt ?

In circuit A the NMOS1 can conduct some current so that the voltage at "out" can increase. Then VM1 can show a voltage larger than 0 Volts.

I think that in circuit B there is no chance at all of the meter VM2 showing anything but V = 0 Volt. Do you agree?

Update

OP suggested this as a "fix"for circuit B to make it work again

schematic

simulate this circuit

Look carefully at the circuit, note how Drain-Source of NMOS3 and VM2 are in parallel with the battery. The battery is ideal, it outputs Vbat, no matter what. Can NMOS3 then still influence the voltage across VM2?

Also note how "out" is now directly connected to the battery, so what can we then say about the voltage at "out"?

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  • \$\begingroup\$ I do. But what if I connected the + pole of the Bat to the drain of de NMOS3 in Circuit B? (Something like switching from NMOS1 to an closed circuit in Circuit A) \$\endgroup\$ – Vitor C Goergen Sep 4 '18 at 13:46
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    \$\begingroup\$ what if I connected the + pole of the Bat to the drain of de NMOS3 in Circuit B Well, think about it! What would VM2 show. It is now in parallel with the battery so.... And what can NMOS3 do? Note that the battery is an "ideal" battery, it can supply as much current as anyone needs while still keeping its nominal voltage across its terminals. \$\endgroup\$ – Bimpelrekkie Sep 4 '18 at 13:51
  • \$\begingroup\$ I think that this is precisely the problem: I can't see the practical difference between an closed wire and an always-conducting transistor. For me in the case I suggested the circuit would work as a NOT gate, since when Vin = HIGH NMOS3 would conduct and VM2 wouldn't be parallel with the battery no more. \$\endgroup\$ – Vitor C Goergen Sep 4 '18 at 14:00
  • \$\begingroup\$ ...and VM2 wouldn't be parallel with the battery no more. How is that possible? I will draw the circuit change you proposed in my answer. \$\endgroup\$ – Bimpelrekkie Sep 4 '18 at 14:03
  • \$\begingroup\$ I appreciate your help, sincerely. \$\endgroup\$ – Vitor C Goergen Sep 4 '18 at 14:04

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