GPIO state of MCU (AVR) with no supply voltage

Question

In general: what state do the GPIOs of a MCU (an AVR in my case) have when there is no supply voltage and the MCU is "off". Am I right that the pins are floating as there isn't any "reference" for the logic level at all.

In special: I have a bilateral switch (BS) shifting a variable voltage (provided by a DAC) for an analog device (AD). Both the BS and the DAC are controlled by a MCU. As the BS's output will be floating when its input is not set high by the MCU, I need a pulldown at the output to define the low-state. I've attached a simplified circuitry illustrating the scenario.

If the MCU is running, everything is clear: the BS will supply the AD with an analog signal as long as gpio1 is high.

But if (for a reason) the 3.3V power supply is not there, I still need to have a defined voltage at the AD's Ain pin. So if my supposition, that the gpios of an inactive MCU are floating, is correct, the following circuitry should meet my requirements:

• MCU active: gpio2 is configured as low output -> strong pulldown (1k & 10k in parallel equals 0k9) outweighs 100k which leads to a negligible voltage divider. Ain is pulled to low voltage (not ground exactly, but close to it - 0.2V)

• MCU inactive: gpio2 is floating -> weaker pulldown (10k) and not negligible voltage divider (100:10) leading to a defined voltage of 0.9*24V = 2.2V.

I'm quite sure that the circuitry as such makes sense, but if it works or not completely depends on the behaviour of gpios when there is no supply voltage for the MCU. Can this damage the MCU? (I guess not, as long as R1 is high enough)

Answer 1

The simplest way to imagine the MCU pins with no power is like this:

Basically I would say that the input is floating, but if you apply any voltage to that pin, then it will flow through the upper protection diode and begin parasitically powering the circuit.

What's going to happen in your circuit, is that once the voltage increases past the diode threshold (0.6v), current is going to start flowing through that 1k, and the voltage isn't going to get much higher than that. Without doing the math, i'd say like.. 0.8v

I'm not sure what exactly the purpose of the gpio2 pulldown is, but you could hook it up like this instead:

^{simulate this circuit – Schematic created using CircuitLab}

Answer 2

No, the inputs are not floating, and yes, applying a voltage to them when power is off can lead to damage. This is true for just about any modern IC, where the data sheet does not explicitly say otherwise.

In the case of say an ATmega328p, we can see it in the "Absolute Maximum Ratings" section

Voltage on any Pin except RESET with respect to Ground . -0.5V to VCC+0.5V

These limits are typically due to the presence of ESD protection diodes which divert currents on the I/O pins to the supply rails. When the supply rail is at ground potentially, the allowed input range is just less than a diode drop higher or lower. Applying a higher voltage (at least without large series resistance) would cause the protection diode to conduct, and could easily provide enough current to damage it. Additionally, it would attempt to raise the entire board's supply net. Even if this did not cause damage it can lead to putting various circuitry into a state from which power on reset would not cleanly work (for example, while it's not a problem the AVR seems to have, I've seen other systems which would not boot if a USB-TTL adapter's data lines were connected before the system was powered, even if that adapter was connected via substantial series resistance)

If you need a defined level, that level should be ground via a pulldown resistor. Even better, also powerdown whatever the MCU is connected to.

Remember also that even if the pin is not floating when power is off, it will be floating between reset and when it is configured as an output. Especially if something like a serial bootloader is involved, that could potentially be a substantial period of time.

Answer 3

One typical problem with unpowered MCU while its GPIO have some path to a voltage rail (like 2.2V from 100k : 10 k divider via R3) is that the MCU power rail will "leak-up" via ESD protection diodes (typically built in GPIO pads). The Vcc voltage rail will be charged up to the input voltage minus 0.5 bandgap diode voltage, minus some leakage via other resistors, hard to predict. Since Vcc will charge up, the "absolute maximum ratings" will unlikely to be exceeded.

Some part of problem is that usual LDO regulators don't have anything to keep their output at zero when Vin is not there. To keep the LDO output down, there are special models with "output discharge", or you need to add explicit bleeding resistors on Vcc rails.

I didn't analyze the exact path in your design, but I hope this answer will give you an idea where to look.

ADDENDUM1: There is a classical example when an un-powered CMOS IC (like CD4017 counter) would even function and count states if just a clock is applied, say a 5-V clock. The Vdd rail will charg up to 4 - 4.3 V level via upper ESD diode, and the counter will happily toggle.

ADDENDUM2: Similar effects frequently occur if an unpowered MCU is connected to a powered interface (say, I2C pull-ups, or USB). The MCU rails might be charged up partially, to some intermediate (1 - 2 V) level. When powered back, the ICs internal circuitry might fail to receive valid internal reset and fail to function properly. This is the major reason why self-powered USB devices are prohibited from any active "back driving" when the host is in unpowered state.