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I am trying to do some hspice simulation with some free 45nm CMOS transistor models. I found that an inverter can simulate properly with voltage as low as 0.25V, though it's slower. My question is, in a controlled environment when speed is not a concern and the device is shielded, can such device run correctly at such low voltage?

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    \$\begingroup\$ subthreshold logic is an area of renewed interest for ultra low power. Old cmos watch chips were subthreshold, and Ambiq Micro makes rtc's and ARMs using it. Look up some of the papers. \$\endgroup\$
    – Henry Crun
    Sep 6, 2018 at 1:51
  • \$\begingroup\$ Hi Kelvin, welcome to EE.SE. I've recently seen some 5v logic chips (CMOS SRAMs) battery-backed by a diode and 3.6v lithium cell. The datasheet specified VINmin as 4.5v, but they happily retained data a volt under that for years. (Iq = < 10µA,.) \$\endgroup\$
    – rdtsc
    Sep 6, 2018 at 2:48
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    \$\begingroup\$ Eric Vittoz of Switzerland is credited with re-vitalizing the Swiss watch industry, by showing how CMOS of the 1970s era could be used in FlipFlips and in nanopower Quartz Crystal oscillators. Vittoz provided analysis of the startup conditions for such oscillators, suggesting GM was the key parameter; he seems to have ignored the slight amounts of phase shift needed, that provided by Rout of CMOS amplifers. He also the one of the people behind the EKV mos transistor model, being charge-accurate simulation to the industry. \$\endgroup\$ Sep 6, 2018 at 3:59

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Yes, as long as you are willing to make transistors with very low threshold voltages then the circuit will work. You can also adjust the thresholds dynamically using a back-gate bias.

However, the subthreshold leakage current will cause your logic to consume considerable dc power.

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