# Can this circuit produce 0, 5 and 12 volts in fixed increments for the AT89LP4052?

Due to the speed requirements of my project, I'm looking at replacing the AT89C4051 with an AT89LP4052 with some code modifications since it offers double the memory and 6x the speed for the same crystal.

I'm in the process of making a parallel port programmer for it. Since the port has only 4 output lines (other than data), I'm trying to save some wires in my design and I'm trying to come up with a good circuit that satisfies the strict requirements to prepare the IC for programming.

The following has been taken from page 61 of the datasheet:

Power-up Sequence
Execute the following sequence to power-up the device before parallel programming.
1. Apply power between VCC and GND pins.
2. After VCC has settled, wait 10 µs and bring RST to “H”.
3. Wait 2 ms for the internal Power-on Reset to time out.
4. Bring P3.2 to “H” and then wait 10 µs.
5. Raise RST/VPP to 12V to enable the parallel programming modes.
6. After VPP has settled, wait an additional 10 µs before programming.

Power-down Sequence
Execute the following sequence to power-down the device after parallel programming.
1. Tri-state P1.
2. Bring RST/VPP down from 12V to VCC and wait 10 µs.
3. Bring XTAL and P3.2 to “L”.
4. Bring RST to “L” and wait 10 µs.
5. Power off VCC.


I want to satisfy both of the above requirements automatically in my circuit without using an external switch, button, jumper, or any other control pin.

I came up with the following:

The idea behind this is that both CLK inputs on the IC are simultaneously driven together by an external clock running at 50Khz (Let's say a 555 timer in astable mode). The POWER_STATE input (to the first D line) is meant to do just that... turn the output voltage from 0 to 5 then to 12 every 20uS then be stuck on 12V. When D = 0 then voltage goes from 12 to 5 then to 0 every 20uS.

The transistors are both 2n3904 but somehow I feel something is wrong with this circuit.

Question is, Is this circuit OK? and if so, is 50Khz an OK clock frequency or would it produce interference during chip operation?

And could this circuit be simplified more with common components?

• How much current is drawn from VPP at 12 V? It could be non-trivial since this is probably used for EEPROM programming. – The Photon Sep 6 '18 at 5:20
• Yes it is for that. When I made my AT89C2051 programmer, I followed the circuit at oocities.org/dinceraydin/8051/index.html – Mike Sep 7 '18 at 3:14