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In the top level of a module, I have the following block:

   genvar i;
   generate 
      for (i = 0; i < DEPTH; i++) begin
       fifo_element #(WIDTH) element (.clk(clk), 
                       .d_in(e_qd[i]), 
                       .d_in_strobe(e_in_strobe[i]), 
                       .q(e_qd[i+1]),
                       .q_ready(e_qready[i]), 
                       .in_strobe_chain(e_in_strobe[i+1]), 
                       .q_out_strobe(e_out_strobe[i+1]), 
                       .out_strobe_chain(e_out_strobe[i]),
                       .prev_used(i == 0 ? 1'b0 : e_used [i-1]), 
                       .next_used(i == DEPTH-1 ? 1'b1 : e_used [i+1]), 
                       .used(e_used[i]));
    end // for (i = 0; i < DEPTH; i++)
   endgenerate

When I attempt to compile this with icarus verilog (v10.1, using the -g2009 command line option) I get the following errors:

fifo.v:84: syntax error
fifo.v:96: error: invalid module item.
fifo.v:97: syntax error

These errors correspond to the line containing for, the last line of the element instantiation, and the line containing the end that corresponds to the begin of the for block. If I delete the apparently-unnecessary begin and end markers the third error goes away but the other two remain.

What's wrong with my code? Or is this a problem with Icarus Verilog? (A little research suggests that while earlier versions didn't support generate blocks at all, they've been supported for some time now, so what I'm trying to do here should work)

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Maybe you need i = i +1 instead of i++. Other than that, I don't see anything obviously wrong.

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  • 1
    \$\begingroup\$ This is it. Apparently the ++ operator is only supported in procedural code (i.e. testbenches) and not in anything that is part of synthesis. \$\endgroup\$ – Jules Sep 7 '18 at 8:23
  • \$\begingroup\$ @Jules: It is most likely that your synthesis tool does not support the ++ operator. \$\endgroup\$ – toolic Sep 10 '18 at 13:41
  • \$\begingroup\$ @toolic - it definitely does, in other contexts, which is what confused me ... I've used it extensively in testbench code without any error. \$\endgroup\$ – Jules Sep 10 '18 at 18:41
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My guess is that you need to explicitly enable verilog 2001 features. I don't know what icarus is, but all the commercial tools I've used require a switch to enable v2k or 2001 or whatever the tool calls it.

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  • \$\begingroup\$ That's the -g command line option: I've tried -g2001, -g2005, and -g2009, all of which should support it. AIUI, the 2005 variant is the default. \$\endgroup\$ – Jules Sep 7 '18 at 4:17

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