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I saw in some PCB stack-up design, sometimes there are two adjacent signal layers, such as:

SIG

GND

SIG

SIG

PWR

SIG

I think there must some crosstalk between them, so how much should be enough of the distance between the two layers to minimize the crosstalk?

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  • \$\begingroup\$ Cross-talk is not a big problem if you use a good stackup as shown by laptop2D and also maintain X and Y separation between the inner signal layers. In other words, the signals will not have much cross-talk unless they are run close together for long stretches. \$\endgroup\$ – mkeith Sep 7 '18 at 6:27
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It depends on what the signals are.

In a 6-layer PCB, you've probably got quite a lot of parallel buses to get from place to place. So common technique is to route each of the two adjacent signal layers with tracks perpendicularly as much as possible; one of the layers predominantly 'north-south', and the other layer predominantly 'east-west', avoiding parallel runs in close proximity as much as possible.

If that isn't significantly possible, and if the signals are significantly likely to cross-talk to others, then physical separation (in the X/Y plane) can be important.

This can be critical for some combinations of signals: high-speed clocks, high-impedance inputs, analog circuitry, high current loops, etc. Sometimes it's just not possible to keep them separated in X/Y enough, and you might have to give priority to some of these signals being on outer layers where they have the ground/power-plane between them and everything else on other layers.

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This is actually not that bad of a layout because the middle prpeg layer is normally the thickest. Because capacitance between two conductors is determined by the area and the distance between the conductors, the middle layer maximizes the distance. In fact it increases the distance by a factor of 4-8 which means 4 to 8 times less capacitance between layers in the middle of the PCB by using this stackup. Less capacitance also means less cross talk as it is the primary means of signals jumping the board.

$$C=\frac{\epsilon_0\epsilon_r A}{d}$$

enter image description here
Source: http://www.bitweenie.com/listings/standard-4-and-6-layer-pcb-stackups/

Henry W Ott (who wrote the book on EMC) recommends another stackup:

Another excellent performing six-layer board is shown in Fig. 8. It provides two buried signal layers and adjacent power and ground planes and satisfies all five objectives. The big disadvantage, however, is that it only has two routing layers -- so it is not often used.

  ________________Ground/ Mounting Pads
  ________________Signal
  ________________Ground
  ________________Power                                  Figure 8
  ________________Signal
  ________________Ground

It is easier to achieve good EMC performance with a six-layer board than with a four-layer board. We also have the advantage of four signal routing layers instead of being limited to just two. As was the case for four-layer boards, it is possible to satisfy four of our five objectives with a six-layer PCB. All five objectives can be satisfied if we limit ourselves to only two signal routing layers. The configurations of Figures 6, 7, and 8 all can all be made to perform very well from an EMC point of view

Source: http://www.hottconsultants.com/techtips/pcb-stack-up-3.html

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  • \$\begingroup\$ Yes, my question take a 'classic' six layer as example. And there are 8 layer, even 10 layers stackup, also have adjacent signal layers, with same total board thickness, this means the adjacent layer will go closer, right? \$\endgroup\$ – diverger Sep 7 '18 at 7:14
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If you know the impedance of the vulnerable node (as resistor plus parallel capacitance, modeled), then inject 1pF from your cross-over signal and compute if this HIGH_PASS behavior is a problem.

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