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I have a circuit based on a P-FET which shall limit inrush current (20 mA). However, when turning on the power supply there is always a current peak (30 mA, 5 ms) through the M1. Even if I tie its gate to the source.

My question is: What effect is causing that current peak?

  • Is the P-FET initially conducting?
  • Is there a capacitance in series with the P-FET which could be large enough to let that current pass?

Appreciate any hints. If there are details missing in my description, my apology in advance.

schematic

simulate this circuit – Schematic created using CircuitLab

@WhatRoughBeast I have updated the FET type.

In order to detail my last comment about counteracting the condition which leads to initial FET conduction (capacitive voltage divider) I'd like to draw what I have in mind. Maybe that helps to understand and discuss about.

schematic

simulate this circuit

So theoretically one would need a charge pump in order to cancel the inrush current through Cgs so no significant (less than Vgs_th) Vgs would develop. The charge pump would need to be very fast.

What do you/others think?

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    \$\begingroup\$ IRF9530 is the default part number for a p-type MOSFET. What are you actually using? Edit your post, edit your schematic, then double-click on the FET and enter the number in the appropriate field. \$\endgroup\$ – WhatRoughBeast Sep 7 '18 at 12:33
  • \$\begingroup\$ Yes there will be an instant when the current is very large due to drain-source leakage mitigated by rise time of the power supply voltage. Voting to close as Op isn't answering comments and it gets very boring when this happens. \$\endgroup\$ – Andy aka Sep 7 '18 at 17:33
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    \$\begingroup\$ @Andyaka - We do not all live in the same time zone as "Stowoda", or you. If I can believe the numbers shown, you made the "isn't answering comments" comment 6 hours after the question was asked. || I suggest you may need to better consider the " stowoda is a new contributor. Be nice, and check out our Code of Conduct." suggestion. Maybe I do too ? :-) \$\endgroup\$ – Russell McMahon♦ Sep 7 '18 at 20:31
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    \$\begingroup\$ @Andyaka 19 now, here in NZ. In another 3 or 4 or so it will be 1 day since he posted, so the same time of day as when he posted. If he has less of a life than some (and more than many here :-) ) he may check daily. I'd be immensely surprised if the SE higher powers thought that 1 day delay, or even several, was a marvellously good reason to vote to close - especially for a new new user with 'Be nice' request officially attached to the post. If you want to feel fulfilled go and downvote something of Olin's. Or mine :-). \$\endgroup\$ – Russell McMahon♦ Sep 8 '18 at 8:25
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    \$\begingroup\$ @Andyaka - Reset / NMI / .... \$\endgroup\$ – Russell McMahon♦ Sep 10 '18 at 7:35
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Since you dont have any specs, no solution is [perfect.] = will meet spec. Perhaps consider a Current sense cct amp. to drive the gate is what you need. These are just ideas, not proven ccts.
- i.e. extremely dependent on load, Vt and RdsOn.

schematic

simulate this circuit – Schematic created using CircuitLab

I changed it to a 240mA load.

But in your case, the ESR of your C1 is greater than the ESR of the Miller Capacitance of your FET

or try this instead to allow slow Vgs turn on.

Rev A

schematic

simulate this circuit

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  • \$\begingroup\$ by any chance missing a cct with a capacitor between gate and drain ? \$\endgroup\$ – JonRB Sep 7 '18 at 13:22
  • \$\begingroup\$ Almost.. Gate and Source with series R to Vgs(th)min \$\endgroup\$ – Tony Stewart EE75 Sep 7 '18 at 13:46
  • \$\begingroup\$ :) not positive feedback then. main point was no cct :) \$\endgroup\$ – JonRB Sep 7 '18 at 13:54
  • \$\begingroup\$ syntax on initial schematic copy \$\endgroup\$ – Tony Stewart EE75 Sep 7 '18 at 13:54
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    \$\begingroup\$ @Tony EE rocketscientist: I am surprised by your circuit suggestion because I actually am thinking that the problem lies with the capacitive voltage divider formed by Cgs + Cgd + Cload. In other words this capacitive voltage divider yields a Vgs which rises above the Vgs_threshold and lets the FET conduct. If that is true, then I would need to add a capacitance in parallel to Cgs in order to "adjust" the capacitive voltage divider so the most voltage drops across Cgd (compared to Cgs drop). Please correct me if I am wrong. Regards. \$\endgroup\$ – stowoda Sep 10 '18 at 8:34

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