Thanks in advance to anyone who will take the time to read my first post here.

At present, I am doing a simulation of a power amplifier in LTSPice. The schematic and relevant files are uploaded in a zip file attached herewith. I have designed a PCB based on this design. I have used 15 V for gate biasing and 15-20 V (Vdd) for drain biasing in the uploaded schematic. The channel is on when gate voltage reaches about 2.1 V. I am using a function generator driven 1.5 V peak to peak sine signal having 7 MHz frequency (AC transient analysis shows around -4 dB gain at this frequency). From the ac transient analysis, I can see that in this configuration I am getting 0.9 V peak to peak at the output in the simulation. Another observation is that as Vdd is increased, gain also increases.

However, in the practical circuit, I am not getting any output, just noise. Even when I increased Vdd upto 25 V, I did not get any RF output. I know I am doing some mistakes which I am not being able to identify so far. I would really appreciate if anyone can provide suggestions.

Thanks in advance. enter image description here

  • \$\begingroup\$ Since you did not mention any physical parameters of PCB or component types, I suspect you must examine this and verify the values of reactance and Q of your components ,trace impedance etc \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 7 '18 at 19:58
  • \$\begingroup\$ Hi Tony, Thanks for the comment. The 2-layered PCB itself is 100mm*80mm in dimension with 2 oz copper thickness and have a solid ground plane. I used COG/NPO type capacitors and fixed inductors. I was thinking about what might have been done better from the simulation point of view so that those changes can be reflected in the actual pcb later. Thanks again. \$\endgroup\$ – Allison_81 Sep 7 '18 at 20:13
  • \$\begingroup\$ Verify each section with a probe and sweep generator to understand the transfer function . If the elements are not reacting the way you expect, then find out how they react at various nodes. Pull C11. Pull the drain to a linear pull up to 5 or 12V like 100 Ohms and probe it for gain. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 7 '18 at 23:23
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    \$\begingroup\$ C11, C12 look reversed \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 7 '18 at 23:25
  • \$\begingroup\$ I have not analyzed each reactive part impedance, but you can by marking this chart to see the impedance ratios in your mind and what to expect. electronics.stackexchange.com/questions/276538/… If Vgs controls Ids when you reduce it then assume the FET is working and set for the threshold you want. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 7 '18 at 23:32

The impedance of C13 (100pF) is quite high at 7MHz (Xc = 1/(w·C) ~ 230 Ohm). Could you try to replace that by a 1nF capacitor?

  • \$\begingroup\$ I also would take care with C2 and C11... C11 should be placed after the inductor L5, right? \$\endgroup\$ – Andrés Martínez Mera Sep 9 '18 at 7:18
  • \$\begingroup\$ Hi Mera, Thanks for the feedback. I have replaced the 100 pF capacitor with a 10 nF capacitor for C13. Can you kindly explain a bit about the positioning of C11? I am using C11 and C12 as RF bypass capacitor. Thanks in advance \$\endgroup\$ – Allison_81 Sep 10 '18 at 17:42
  • \$\begingroup\$ Well, I usually work in the UHF band, but the working principles must be the same. C11 is quite a low impedance at 7MHz (Xc = 1/(w·C) = 4.83Ohm). This means that the energy flows through it to ground (you're almost shortcutting the output). That C11 is typically placed after the choke, L5, whose inductance should be enough to behave like an open circuit at RF. In this case, I think L5 is quite low... 180nH @ 7MHz => XL = 7.9Ohm. In my opinion, L5 should be something like 33uH or so... I assumed that you're designing a class A PA, but to my mind, these values are a bit weird. \$\endgroup\$ – Andrés Martínez Mera Sep 11 '18 at 15:13
  • \$\begingroup\$ Hi Mera, Thanks for the valuable comment. To be honest, I am new in the design of PA and in HF, VHF range. So, I am finding all the comments greatly helpful. I can see what you are trying to point out. I will modify the circuit accordingly to see the response. \$\endgroup\$ – Allison_81 Sep 11 '18 at 16:48

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