Why is this a standard for AND gates
when it could be made with two FETs and a resistor instead?
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In order to get non-inverting operation for logic (i.e., AND or OR vs. NAND or NOR), you need to operate the transistors in common-drain mode, also known as "source follower" mode.
Among the problems with this mode for logic:
Together, these issues mean that you cannot connect the output of this gate to the inputs of another copy of itself. This makes it rather useless for building more complex circuits.
This is why all successful logic families1 are built using transistors in common-source (or common-emitter) mode, which has significant voltage gain and no cumulative offsets between inputs and outputs — but the output is inverted with respect to the input. Therefore, the basic functions include an inversion: either NAND or NOR.
As a bonus, NAND and NOR gates are "functionally complete", which means that you can build any logic function at all (including storage elements such as latches and flip-flops) from all NAND gates or all NOR gates.
1 To be specific, logic families that use voltages as logic states. This includes RTL, DTL, TTL, PMOS, NMOS and CMOS. Current-mode logic families such as ECL do indeed use a combination of emitter followers and common-base transistors to achieve the same ends while avoiding saturation (for speed).
What you're describing is PMOS logic. It has some significant disadvantages over CMOS:
If the value of the resistor is low, the gate will consume a significant amount of static power when the gate is active. CMOS gates consume essentially no power when they are not actively switching.
If the value of the resistor is high, the gate is slow to turn off, because the capacitance of any gates driven by the output must be discharged through the resistor. Additionally, a high-value resistor will likely consume more area than a set of complementary transistors would.
For process-related reasons, PMOS is less efficient than the inverse -- NMOS logic.
A reason I don't think anyone mentioned yet: Technology constraints:
Resistors on chip are massive compared to transistors. To get a decent value, we are talking orders-of-magnitude bigger than the smallest transistors. In other words, next to all the other advantages you get with proper CMOS (static current, drive levels, output swing), it is also just a lot cheaper.
Patterning: The transistors on logic can be that small because they are patterned in a repetitive way. This also allows them to get higher yields and more consistent performance. Throwing in resistors would ruin this.
Capacitance: The limitation of speed in a logic system is the capacitance of the next stage. More capacitance means slower (less performance) or more drive strength needed (bigger transistors, more area, more static current, more power consumption, more capacitance presented to the preceding stage). A big resistor will probably give you a lot of capacitance to charge up as it takes up a physically large area. This could hurt performance.
This is sometimes done on more specialized technologies where you might not have good logic transistors (for analog/RF applications).
Transistor resistor logic is a field of knowledge. The properties of logic gates that rely on resistors are very different than the properties of those which use transistors. For one, pulldown resistors which are kept in the high state continuously dissipate power. This can be a problem for battery powered or high-density designs. Same applies the other way around (for pulldowns held low).
Another area where there is a big difference is in speed and drive strength. The push-pull output structure used in CMOS can switch rapidly without dissipating power when static.
Please note that the circuit you drew will not work at all. You cannot put NMOS in the top branch unless the input voltage is higher than VCC. If the output has much of a load at all, your circuit will not be able to drive anywhere near VCC. It may not even be high enough to be recognized as "high" by some logic gates.
This is not just a nitpick. As it turns out, it is very hard to build something that switches rail-to-rail in one stage unless it is inverting in nature (as NAND and NOR are). And this is the real reason why AND gates use NAND followed by NOT (inverter). Nobody in the world knows a way to make a general purpose CMOS AND gate with fewer than 6 transistors. Same applies to OR.
A major reason in TTL logic, and I would suggest in most logic families, is that the gain element is inverting. To have a non-inverting output with good drive characteristics requires an additional inverter.
This inverter is a bad thing.
Since we are usually fighting speed with discrete gates (or we were when they were the only choice), inverting gates ruled the day. Non-inverting gates were available (compare the 7400 with the 7408).
The main exemplar of this is the and-or-invert gate. For typical TTL numbers, the propagation delay is the same as NAND and NOR, but it includes two levels of logic.
The advantages of using a CMOS design are many:
So a NAND gate followed by a inverter is used to design an AND gate.
Building an AND out of a NAND allows one to use minimal gate sizes for the logic and size the two (and only two) transistors in the inverter to drive the line. This maximizes speed and minimizes power loss at the expense of only a little more area used for the additional transistors (accounting for the size of the resistor needed to drive the line in the intended application).
Also, to share some wisdom I learned in college (a long time ago in a galaxy far, far away...): We once enjoyed a presentation about gate-array logic. At the end, a student asked why an engineer should bother minimizing the number of NAND gates used when all those NAND gates were on the chip in the first place? The presenter's answer has stuck with me for 30 years: because if we don't, our competitors will.
If your competitor can make a faster and more power efficient circuit with no appreciable difference in cost, then using the resistor is a commercial mistake, not just an engineering mistake.
A logic signal which passes through a non-amplifying gate will end up significantly weaker than it was to start with. While one could include a non-inverting AND gate within a chip, gates fed by the weak output would likely switch so much more slowly than gates fed by gates fed by a strong output that the time required to pass a signal through a NAND, inverter, and one other gate, would likely be less than if the NAND and inverter were replaced with a weak-output AND.
Note that even if one has both NMOS and PMOS transistors available and wanted to build a weak-output AND gate, one should construct the gate in a fashion similar to a CMOS NOR gate, but reversing the NMOS and PMOS transistors, so as to avoid static power dissipation. Resistors are very expensive, so one should avoid using them unless absolutely necessary.
A point that hasn't been mentioned in other answers, however, is that an inverting gate can contain a mixture of series and parallel outputs. For example, one could have a practical complex gate that computes "not ((X and Y) or (X and Z) or (Y and Z))" using only one level of inversion. Although it's not practical to have an "AND" which feeds its output to multiple places in a circuit, one can include an "AND" gate on one or more inputs of a "NOR" gate, or an "OR" gate on one or more inputs of a "NAND" gate.