This is just a note on your AND gate design. You can use CircuitLab's simulator to help understand your circuit.
simulate this circuit – Schematic created using CircuitLab
Figure 1. The simulator needs a circuit GND as a reference for its calculations. I've added it to supply negative which is the usual location.
Figure 2. The original circuit.
With the addition of some nodes for voltage measurement the DC Solver shows us that when both transistors are on that the most current through the LED will be about 0.4 mA. This is mostly due to the voltage drop across R1. You can add in another node on the LED to check what voltage it is seeing.
Note the voltage drops between NODE1, NODE4 and NODE5.
Figure 3. R1 has been reduced to 100 Ω.
Now, at least, we get 7 mA through the LED and it should be good and bright.
Notice that there is a significant voltage drop on each transistor of about 0.7 V each. You have only 2.5 V on your output. You should be able to see that this isn't going to scale well for a 3 or 4-input AND gate.
You can experiment with the simulator in your schematics to understand further what happens when you disconnect one of the inputs. Don't forget to add a GND.
At least one of the other answers has pointed out that the load should be in the collector side of Q1. The reason is that the transistors can be driven into saturation and the voltage drop across each is very low.
Figure 3. Low-side switching results in much lower voltage drop across the transistors.