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I am developing 4 layer PCB with following general stack up:

Layer 1: Signal Layer (top side)
Layer 2: Ground Plane
Layer 3: Power Plane
Layer 4: Signal Layer (bottom side)

For Layer 1 & Layer 4 which internal layer to be considered as a reference to calculate characteristic impedance?

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A power plane should be an AC ground. It is if you've done it correctly, and it's not worth having if you haven't. A real ground is automatically an AC ground.

Reference outer layer signal tracks to the nearest AC ground layer. This configuration is called microstrip.

If a signal track is sandwiched between two AC ground layers, calculate the characteristic impedance with respect to both grounds. This configuration is called stripline, and has about half the impedance for the same width and ground spacings.

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    \$\begingroup\$ Perhaps answer the question a little more clearly: Yes, the power plane is used for impedance calculations. \$\endgroup\$ – Timmy Brolin Sep 8 '18 at 8:44
  • \$\begingroup\$ @Neil_UK in my design there is a single GND net (Ground Plane) and one power plane. GND plane is fully copper filled and without discontinuities. Power plane is with different power domains seperated from each other. My Layer 4 is closer to power place instead of GND plane. Hence I would like to know which plane should I consider for Microstrip trace characteristic impedance calculation? Is it nearest power plane or far GND plane? As per my understanding engineer do characteristics impedance calculation w.r.t. GND plane (i.e. return patch for any signal / electromagnetic wave) Please help! \$\endgroup\$ – Akky Sep 10 '18 at 13:15
  • \$\begingroup\$ @TimmyBrolin : Thanks for help. In my case power plane is broken in multiple power domains such as 3.3V; 1.8V & 5V etc. seperated from each other. Each domain is copper filled area. This plane (Layer 3) is near to Signal Layer (Layer 4) & GND plane (Layer 2) is far from layer 4. So should I consider GND plane as reference plane instead of power plane as it is uniform layer without any copper discontinuities? \$\endgroup\$ – Akky Sep 10 '18 at 13:21
  • \$\begingroup\$ Always the nearest plane. And no, you do not want discontinuities in a plane used as reference for impedance controlled signals. \$\endgroup\$ – Timmy Brolin Sep 17 '18 at 21:21
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It is worthwhile to note that track impedance is halved by reducing the dielectric thickness permitting narrower tracks for ease of routing.

Also for decoupling very special thin dielectric prepreg and smooth copper is useful for low ESR high C power planes. Both V+ and 0V are RF ground planes as these ought to be near 0 Ohm ESR RF impedance.

Take note of the track width to thickness w:t for the laminate carefully. You can choose these to be the same or different to achieve any standard thickness or custom.

For 50 Ohms microstrip w:t=3:2 ratio is close and for stripline w:t=2:3 and for microstrip differential pair is also like crosstalk so beware of long equal track gap crosstalk at high impedance and get a good calculator like Saturn PCB Design Inc's

Choosing the signal layers on the outside is best for DFT access to test points. But unintentional RF radiation can increase which may cause issues from single ended tracks in the 50 to the 200MHz range.

  • Choosing differential CML is best for speed.
  • 74HC outputs at 5V are >= 50 Ohms +/-25% (est.)
  • 74ALC outputs like ARM @3.3V are ~ 25 Ohms +/25% (est.)
  • Verify this using a VNA or use Vol/Iol results verified from the datasheet.
  • Avoiding Blind or Buried vias are recommended unless necessary and in high volume.
  • choose Polyamide or Getek or FR4 rated 1GHz or when rise times <4ns or thereabouts for dielectric loss tangent reasons for best signal integrity.
  • PCB, Dk effectively reduces with frequency >= 1GHz This can cause young RF expert designs to do several prototypes spins before tolerance effects on filters before they get it right.
  • balance the copper distribution to avoid lamination warpage.

  • consult with PCB board shops for online design rules for optimal cost and yield

  • Do you own design research! I just wrote off the cuff reported my experience.

  • Investing in educating yourself on DFT, DFM and DFC before attempting a design by due diligence and research is well worth the time and money saved in design faults.

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  • \$\begingroup\$ Hi Tony, Thanks for your valuable reply. But I it couldn't help me to understand 'If a signal layer is between GND layer & power layer (e.g. GND layer <-> Signal Layer <-> Power Layer); which layer I should consider for characteristic impedance calculation of signal layer & why? Because I as per my understanding; generally engineers consider GND plane as a reference to signal layer to calculate characteristic impedance of traces on that layer. **Note: In my PCB design I am using single GND (Ground) net in GND layer (fully copper filled layer with no discontinuities). \$\endgroup\$ – Akky Sep 10 '18 at 13:08
  • \$\begingroup\$ The layer choice for Gnd depends on heat dissipation and via inductance and slew rate of V and I. etc, so it depends. Generally for good decoupling a power plane is just as important as gnd plane to reduce ringing or voltage drop with synchronous loads, but you cct needs may differ. \$\endgroup\$ – Tony Stewart EE75 Sep 11 '18 at 0:13

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