It is worthwhile to note that track impedance is halved by reducing the dielectric thickness permitting narrower tracks for ease of routing.
Also for decoupling very special thin dielectric prepreg and smooth copper is useful for low ESR high C power planes. Both V+ and 0V are RF ground planes as these ought to be near 0 Ohm ESR RF impedance.
Take note of the track width to thickness w:t for the laminate carefully. You can choose these to be the same or different to achieve any standard thickness or custom.
For 50 Ohms microstrip w:t=3:2 ratio is close and for stripline w:t=2:3 and for microstrip differential pair is also like crosstalk so beware of long equal track gap crosstalk at high impedance and get a good calculator like Saturn PCB Design Inc's
Choosing the signal layers on the outside is best for DFT access to test points. But unintentional RF radiation can increase which may cause issues from single ended tracks in the 50 to the 200MHz range.
- Choosing differential CML is best for speed.
- 74HC outputs at 5V are >= 50 Ohms +/-25% (est.)
- 74ALC outputs like ARM @3.3V are ~ 25 Ohms +/25% (est.)
- Verify this using a VNA or use Vol/Iol results verified from the datasheet.
- Avoiding Blind or Buried vias are recommended unless necessary and in high volume.
- choose Polyamide or Getek or FR4 rated 1GHz or when rise times <4ns or thereabouts for dielectric loss tangent reasons for best signal integrity.
- PCB, Dk effectively reduces with frequency >= 1GHz This can cause young RF expert designs to do several prototypes spins before tolerance effects on filters before they get it right.
balance the copper distribution to avoid lamination warpage.
consult with PCB board shops for online design rules for optimal cost and yield
Do you own design research! I just wrote off the cuff reported my experience.
Investing in educating yourself on DFT, DFM and DFC before attempting a design by due diligence and research is well worth the time and money saved in design faults.