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pulses to be countedI want to design a binary counter in Cadence that counts pulses in every consecutive 50 nano seconds but i want it to be reset at the end of each 50 ns and shortly - so that it doesn't miss any pulse - start counting again. What do I need to add to a basic JK flip-flop like this to make the this kind of reset possible? jkff

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    \$\begingroup\$ I suspect an X-Y problem. How big a counter and what do you want to count? What Cadence? Cadence Verilog , Cadence schematic, Cadence analog sim? Also J-K are nice for education and making complex problems for student but real counters are using D-registers with logic, mostly in FPGAs \$\endgroup\$ – Oldfart Sep 8 '18 at 11:08
  • \$\begingroup\$ @Oldfart I recall making discrete state machines using JK devices ('7476 parts), but that was many years ago (decades in fact). \$\endgroup\$ – Peter Smith Sep 8 '18 at 11:50
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    \$\begingroup\$ I agree with @Oldfart. I was designing chips in the 1980s and we never used anything but D flip-flops. Now I teach and I refuse to talk about JK, Toggle, or any other antique. \$\endgroup\$ – Elliot Alderson Sep 8 '18 at 11:55
  • \$\begingroup\$ Are the pulses you're counting synchronous or asynchronous with respect to the 50 ns reset pulse? \$\endgroup\$ – Dave Tweed Sep 8 '18 at 12:30
  • \$\begingroup\$ @Oldfart Cadence schematics, I want to make a counter with flip flops that are made of gates, and I want to design the gates in schematics using MOSFETs and finally have a binary counter. But I don't know which flip flop is better for such a counter and how can I reset it every 50 ns? I added the pulses picture. please heck \$\endgroup\$ – Fateme Sep 8 '18 at 18:42
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The solution to prevent metastable (race) and clock speed issues is a fast sync prescaler design. Your specs need to be defined before any design , discrete FF or otherwise IC choice may begin.

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