1
\$\begingroup\$

I understand that when the address input to a parallel EEPROM changes from A to B, the output may show results that aren't the contents of either A or B, for a few nanoseconds.

Are these spurious outputs constrained to be values stored somewhere in the EEPROM?

Would an unprogrammed EEPROM (all 0xFFs) ever output non-FF values when the address changes?

(I expect the specs say that any value could be output, but I'm interested in what happens with current implementation technology.)

I'm asking because I have two EEPROM bits which will cause a bus conflict if they are ever both 0. There will be no value stored at any address in the eeprom which has both bits as 0.

\$\endgroup\$
1
\$\begingroup\$

If the output is latched, and if the timing constraints (address stable before latch) are observed, then that should not happen.

If there’s no latch, then allowing the minimum delay to occur after the address lines are stable before enabling the chip will typically suffice. Eg. see the timing diagram for the 28C64 (Fig.3)

If you’re just wiggling the address lines around, the the output may not do what you don’t want, but it certainly could.

\$\endgroup\$
  • \$\begingroup\$ Yes, I'm just wiggling the address lines around, while CE# and OE# are low. \$\endgroup\$ – fadedbee Sep 9 '18 at 8:16

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.