I've seen a couple of very similar questions but the answers don't answer my question:

DDR2 CAS Latency - is it fixed to clock-cycles or time?

What limits the lower bound of DRAM CAS latency

In my current understanding once a row in DRAM bank has been activated then it's just a matter of the values registered on the amplifiers to be latched out to the output and this process is synchronized by the clock, so it should be specified in clock cycles how long it takes to read a column from an active row.

Yet it appears CAS is time-based, e.g. this datasheet has CAS=1 for 166MHz, CAS=2 for 100MHz, CAS=3 for 50MHz and has CAS configurable, which in my understanding should be a constant number of clock cycles regardless of the clock frequency.

What is wrong with my understanding? What analog process the column reads in DRAM depend on?

Edit: researching on this a bit more I've found there's t_CAC, the time between the CAS pin is driven low and valid data is available on the data pins. Then t_CAS is always measured in a whole number of clock cycles and should be t_CAS >= t_CAC. This makes me think the read process is actually asynchronous with purely combinational logic in between the sense amplifiers and the CAS pin and the data pins. Is this correct?


1 Answer 1


Inside the SDRAM chip, the actual CAS latency requirement is a combinatorial time delay, independent of the external interface's clock period. It may help to think of it as an old-fashioned asynchronous DRAM chip "wrapped" in a synchronous interface.

Since the bus master (CPU) can choose the interface clock speed, it makes sense to also allow it to configure the number of clocks to use for CAS latency, in order to get the best performance without dropping below the amount of time the chip requires internally.

  • \$\begingroup\$ I understand this, but the question is why this delay is independent of the external clock. Is this because there is an internal clock with a different set frequency independent of the external clock frequency. \$\endgroup\$
    – axk
    Sep 9, 2018 at 16:14
  • \$\begingroup\$ No, there is no other "internal" clock. The actual RAM array is asynchronous. \$\endgroup\$
    – Dave Tweed
    Sep 9, 2018 at 16:15
  • \$\begingroup\$ I understand that before and during a row activation it's asynchronous, but when a row is active and we're reading from the active row, is't this read process all synchronous? \$\endgroup\$
    – axk
    Sep 9, 2018 at 16:19
  • 1
    \$\begingroup\$ No. CAS latency is associated with the last part of the asynchronous row-reading process -- basically, selecting at what time to capture the data coming out of the column sense amplifiers. Clocking out the data after that is synchronous, but that isn't what CAS latency is about. \$\endgroup\$
    – Dave Tweed
    Sep 9, 2018 at 16:25
  • 1
    \$\begingroup\$ In the datasheet you cited, the block diagram and operational descriptions are pretty clear. Note how the minimum clock period varies with the CL setting -- this gives you a clue about the internal access time. \$\endgroup\$
    – Dave Tweed
    Sep 9, 2018 at 18:11

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