# Charging capacitor bank with current limiting circuit

I would like to charge a capacitor bank with a 4.8 volt supply that I have. With the help received in response to this question, I now have a a useful current limiting circuit (shown below), that allows me to select a maximum current through a load. I have reimplemented the solution in CircuitLab . . .

The circuit is set to give a 480 mA max current. As the load resistance increases, the SER of the limiting circuit drops away. The following plot shows current through the load versus load resistance . . .

However, what happens if I want to charge a capacitor bank using this circuit. Where would I put it? Current needs to flow through R_sense to cause a voltage drop in order for the circuit to function. If I just add a capacitor after the sense resistor . . .

. . . and then measure the voltage across the capacitor, some crazy stuff happens . . .

What am I doing wrong ( -120V .. really )?

EDIT:

Following Oli's advice by adding a leakage resistor and paying attention to initial conditions . . .

.. I now get a logical looking output, although the voltage is not up to Vcc

If I place the capacitor where R_Load is,

Then the voltage of the cap jumps up to 4.8 volts immediately (which I'm guessing would draw a massive current, fry my supply, and negate the point of the current limiting circuit)

This looks pretty logical to me. If a cap is connected to an ideal voltage source, it will get an infinite current and be at 4.8 V instantaneously. What do I need to do in order to reproduce the effect shown in Oli's lowest plot?

• For the second simulation with the cap at the top, you need to set the cap voltage to 0V initially. I did this by setting the voltage at the MOSFET drain to 4.8V, the .ic V(n001) 4.8 you can see next to the cap is the SPICE command to do this. This means both ends of the cap are at 4.8V hence there is no voltage across it. I'm not sure how you do this in Circuit Lab, if you can link to your circuit maybe I (or someone else more familiar with it) can help. – Oli Glaser Sep 5 '12 at 13:03
• circuitlab.com/circuit/t974eh/opamp_cap_charge – learnvst Sep 5 '12 at 13:09
• Okay, thanks. Unfortunately it seems there is no way to do this in CircuitLab yet. They suggest using a time controlled switch switching at T=0 as a workaround. CircuitLab is pretty, but it's not as sophisticated as SPICE - if you are planning on doing plenty of EE, then I'd advise getting to know SPICE (LTSpice is a great free version from LT, there are also other options like NI Multisim, TINA from TI, ngspice, etc) – Oli Glaser Sep 5 '12 at 13:27
• Okay, I managed to use the switch to simulate the initial condition. Try this edited version of your circuit. – Oli Glaser Sep 5 '12 at 13:39
• Wow, thanks for the help Oli! So the current limiter in this case is controlling the discharge rate of the -ve plate. I eventually want to place a load across the cap that might spike huge current (hence the big cap). Would I be better modifying this circuit to us a Pch MOSFET and use high-side limiting? It is the supply that I want to protect, not the load. – learnvst Sep 5 '12 at 14:49

As Madmanguruman says, the capacitor is in the wrong place.

The opamp is trying to keep the voltages on it's inverting input the same as the non-inverting input, which is 240mV in your example above. To do this with just Rsense present, it must keep 480mA flowing through Rsense as you say.
Now, with the cap in series, it will actually work to charge the capacitor as you have it. However, the catch is that it will not be at a constant current, and the cap will only charge to 240mV, since this it what the opamp needs to keep the balance.
The cap does not pass DC, so the current is initially 480mA, and drops exponentially down to 0 as the voltage rises (and the voltage across the resistor drops)

Another thing to understand here is that a simulation is only as real as you make it, and in some cases the ideal components cause problems. It's quite common for the simulator not to converge or produce odd results if there is no DC path available. Also with a transient simulation, you sometimes need initial conditions set to observe a process.
For example, if I simulate the above circuit in LTSpice with an ideal 1F capacitor, the simulation does not converge (never finishes) If I add a high value of parallel resistance (10MΩ, this is actually very conservative for such a large value, probably be much lower) to provide a DC path, and (very roughly) simulate real world imperfect capacitor leakage, the simulation works:

Simulation:

The 240mV is produced by the 24nA across the 10MΩ resistance (24e-9 * 10e6 = 0.24V) However, the cap starts the simulation at 240mV. Is this what will happen in real life? It's unlikely, so we need to simulate things as it will be when power is switched on, or at least with the cap starting with 0V across it. The reason this happens (in SPICE at least) is because there is an initial DC operating point simulation done before the transient simulation starts.

If we do the same simulation with an initial condition specified, we can see the "interesting" bit that happens prior to reaching a steady state:

So remember to be aware of the difference between ideal and real world components. If simulation results appear strange, then try adding some ESR/ESL (equivalent series resistance/inductance) and parallel resistances to simulations that correspond with the components you intend to use (datasheet will give values usually)
Also be aware of tolerances, for which monte carlo simulation is very useful.

Finally, here is the circuit with the cap placed in the right place, (although you may want high side current limiting in your final circuit):

Simulation of current through cap and voltage across it, notice the constant 480mA up until the cap is fully charged to 4.8V (initial condition used again to see the cap charging):

One last thing, make sure you do not use the LM741 in your final circuit, it's completely obsolete. Choose a decent general purpose rail to rail input/output opamp (rail to rail means it can swing all the way to each rail at the output and handle voltages up to each rail at the input, many opamps, including the 741, cannot do this - another departure from the convenient world of ideal components)

• Many thanks for another outstanding answer. However, I cannot reproduce your final figure. See edits for details. – learnvst Sep 5 '12 at 12:55

Current needs to flow through R_sense to cause a voltage drop in order for the circuit to function.

EDIT: After looking a second time at your circuit, I realized that there are some limitations.

The absolute maximum voltage that you'll be able to charge the capacitor to is $V_{out(OA1)} - V_{th(M2)}$ which isn't going to be terribly useful.

$V_{out(OA1)}$ is going to be less than the 4.8V supply, since a 741 op-amp isn't rail-to-rail output. Let's assume it can output 4.8V for now. The worst-case gate-to-source threshold $V_{th}$ for an IRF530 is 4V. This leaves only 800mV of capacitor voltage before the MOSFET will pinch itself off (there won't be enough gate-to-source voltage to keep it turned on).

As you can see, you're able to limit the capacitor current, but the voltage will be very low due to the circuit configuration you have.

The -120V is obviously a simulation 'oops'. The capacitor should start out like a short and ramp up to its final value smoothly.