As I understand from watching overclocking videos, the maximum operating frequency of a digital ASIC is a function of voltage and temperature. Specifically, it seems that the maximum operating frequency increases with higher voltages and lower temperatures.
My guess is that gate delay and routing delay both vary with operating voltage and temperature. Is that correct? Given a process node (e.g. TSMC's 16nm FinFET+) where can I find documentation (e.g. datasheets) explaining how gate and routing delays vary with voltage and temperature?