# Gate and routing delays as a function of voltage and temperature

As I understand from watching overclocking videos, the maximum operating frequency of a digital ASIC is a function of voltage and temperature. Specifically, it seems that the maximum operating frequency increases with higher voltages and lower temperatures.

My guess is that gate delay and routing delay both vary with operating voltage and temperature. Is that correct? Given a process node (e.g. TSMC's 16nm FinFET+) where can I find documentation (e.g. datasheets) explaining how gate and routing delays vary with voltage and temperature?

## 2 Answers

For submicron technologies the gate and routing delay variability maximum operating frequency of a digital ASIC as a function of voltage and temperature is more complex than in classic CMOS. In particular, there is new effect called "ITD", see this academic article

One of such factors is the Inversed Temperature Dependence (ITD) effect 1. When a circuit is operating in low voltage, the propagation delay of a cell may decrease as the temperature increases.

So cooling of a processor does not necessarily help.

For exact details you probably need to contact TSMC, look up their white papers, or look for more recent papers from world SEMICON conferences.

Regarding overclocking, these days must be over: modern 22-14 nm processors employ local embedded LDO regulators that might be set constant but different for different CPU blocks, so external supply voltage has little to no effect on overall CPU performance.

• You seem to be suggesting that routing delay is affected by temperature and voltage. Is that really what you mean to say? If so, can you explain how temperature and voltage affect routing delay? – Elliot Alderson Sep 9 '18 at 21:40
• "look up their white papers" -> Where can I download these white papers? It's frustrating that the documentation seems to not be readily available. – Randomblue Sep 9 '18 at 22:19
• @Randomblue, this is a highly competitive field of engineering, where billions of  are at stake. No one would unfold their technological secrets unless they become kind of common, like IDT, so there are no readily available "documentation" unless you are a sizable customer with signed NDA with foundries. Or you need to fish out publications by associated academical institutions. – Ale..chenski Sep 9 '18 at 23:03
• @ElliotAlderson, low-k materials are not exactly simple ones in electrical properties, there are odd dependencies and non-linearities. But for nit-picking persons I am changing the "gate and routing delay variability" to "maximum operating frequency of a digital ASIC as a function of voltage and temperature". – Ale..chenski Sep 9 '18 at 23:07
• These days you may be able to adjust the LDOs thought. And depending on your ASIC it may very well just use the external power rails. E.g. Texas AM4372 Cortex A9 processor wants FOUR different voltages. That's partially understandable because Texas happens to sell PMICs but still.. They actually give a table of voltage combinations and which frequencies they allow. – Barleyman Sep 12 '18 at 14:46

Some years ago I was involved in writing EDA software, and the process for determining the delay of a specific gate was:

• Obtain the .lib file for the selected technology. See file format: http://www.ee.virginia.edu/~mrs8n/soc/SynthesisTutorials/ct_tlfref.pdf
• Look up the cell model and the specific "arc" you're interested in (input/ouput pin,rise/fall)
• Pick a "timing corner" and voltage/temperature parameters
• Determine a suitable input slew and output load. If you have trouble with this then you can just simplify it to a chain of the same gate to determine a "standard" value.
• Using the linear (or otherwise) model from the library, you can now simply read off what the delay is.

We approximated routing delay with Elmore Delay which worked well enough.

Obtaining the .lib file is a pain; either you need to call their rep (which you'll eventually have to do anyway) or get one of your contacts in the industry to give you one.

Please note that delay is to some extent a yield-based parameter - it may vary by a few percent not only between chips but even between different parts of the same chip. Your search keyword for this is "PVT variability".