As far as I'm concerned, Stackup 2 is a no-go, because it's non-symmetric. The upper thick dielectric layer is 3rd from the top, but the bottom thick dielectric layer is 2nd from the bottom. This can cause warping of the finished boards, which will lead to further problems.
So if these are your only two choices, you should choose stackup 1.
Because I have many power rails, I have to split the PWR plane. So, for continuous transimision impedance, I think may L6 goes closer to L7 will be better than go closer to PWR plane, right?
You don't want your controlled impedance traces to run across a split in the power plane if they're using that power plane for their return current.
If you can arrange your splits to not pass under high speed traces, then you can use the power plane as the return for controlled impedance traces.
If your data rates are not too high (say below 1 Gbps), you can probably get away with passing traces over splits, as long as you provide a capacitive path for the return currents to cross the split as well. This could be a capacitor connecting the two power nets, or capacitors from each of the power nets to ground, located as close as possible to where the trace crosses the split.
Other strategies you might consider:
Dedicate one or two layers to low-speed signals, so that these don't require controlled impedance.
Two high speed layers (assuming not too high a speed) can share a reference plane if one is used for horizontal routes and the other for vertical (so that traces on the two layers don't run parallel each other for any appreciable distance).
I've seen this mainly used to have routing on L1 and L2 with ground on L3. Whether this is viable or not also depends how dense the component placement is on the top layer.
If you really need 5 controlled impedance routing layers, then you may in fact want to pay up for a 10 layer stackup.