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I'm designing a 8-layer PCB stack up. I have two choices as below:

Layer   STACKUP 1    Layer   STACKUP 2   Question related
=========================================================
  1     SIGNAL         1     SIGNAL
  2     GROUND         2     GROUND
  3     SIGNAL         3     SIGNAL
       / / / / /            / / / / /
  4     SIGNAL         4     SIGNAL
  5     POWER          5     POWER
       / / / / /       6     SIGNAL          X
  6     SIGNAL              / / / / /        X
  7     GROUND         7     GROUND          X
  8     SIGNAL         8     SIGNAL          X

The / / / / / means there is a relative wider distance (around 0.5mm). The difference of the two choice is the reference plane of L6, closer to PWR plane 5, or closer to GND plane 7. Because I have many power rails, I have to split the PWR plane. So, for continuous transimision impedance, I think may L6 goes closer to L7 will be better than go closer to PWR plane, right?

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  • \$\begingroup\$ I have always been told that you need to have an even number of power planes (including power and ground). And that they need to be mirror image top to bottom. Can you get by with 4 signal and 4 plane layers? If so, I would do signal, plane, plane,signal,signal,plane,plane,signal. You can figure out which planes should be power and which ground. \$\endgroup\$ – mkeith Sep 10 '18 at 3:16
  • \$\begingroup\$ Then I may go to 10 layer, the cost will increase :(. And I've done the layout, now I can change the layer stackup only. \$\endgroup\$ – diverger Sep 10 '18 at 3:25
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    \$\begingroup\$ Stackup 2 is not symmetric --- which can lead to warping or other issues. \$\endgroup\$ – The Photon Sep 10 '18 at 3:25
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    \$\begingroup\$ I think Stackup 1 is OK. The spacing can be symmetric. Only asymmetry is that layer 4 is a signal layer and layer 5 is a plane layer. Maybe you can make up for it by flooding layer 4 with as much GND copper as possible. Then it will have the same thickness as a plane layer, after the board is fully fabricated. \$\endgroup\$ – mkeith Sep 10 '18 at 3:33
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    \$\begingroup\$ Which layers need impedance control? \$\endgroup\$ – The Photon Sep 10 '18 at 3:51
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As far as I'm concerned, Stackup 2 is a no-go, because it's non-symmetric. The upper thick dielectric layer is 3rd from the top, but the bottom thick dielectric layer is 2nd from the bottom. This can cause warping of the finished boards, which will lead to further problems.

So if these are your only two choices, you should choose stackup 1.

Because I have many power rails, I have to split the PWR plane. So, for continuous transimision impedance, I think may L6 goes closer to L7 will be better than go closer to PWR plane, right?

You don't want your controlled impedance traces to run across a split in the power plane if they're using that power plane for their return current.

If you can arrange your splits to not pass under high speed traces, then you can use the power plane as the return for controlled impedance traces.

If your data rates are not too high (say below 1 Gbps), you can probably get away with passing traces over splits, as long as you provide a capacitive path for the return currents to cross the split as well. This could be a capacitor connecting the two power nets, or capacitors from each of the power nets to ground, located as close as possible to where the trace crosses the split.

Other strategies you might consider:

  • Dedicate one or two layers to low-speed signals, so that these don't require controlled impedance.

  • Two high speed layers (assuming not too high a speed) can share a reference plane if one is used for horizontal routes and the other for vertical (so that traces on the two layers don't run parallel each other for any appreciable distance).

    I've seen this mainly used to have routing on L1 and L2 with ground on L3. Whether this is viable or not also depends how dense the component placement is on the top layer.

  • If you really need 5 controlled impedance routing layers, then you may in fact want to pay up for a 10 layer stackup.

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  • \$\begingroup\$ The core chip of the board is FPGA + DDR3, all the DDR3 track routed in the internal layers, so I think the 8L maybe the bottom choice. And the layer count need controlled impedance can't be reduce any more. Hope it will work without going to 10L :). \$\endgroup\$ – diverger Sep 11 '18 at 0:51

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