pull-push gate driver for H bridge circuit

Question

To drive power MOSFET following circuits with different pros and cons has been used

type A

type B

type C

type c which is called pull-pusher gate driver can used either P or N mosfet

in h-bridge driver, mostly used type A and B for controlling one side P and N type mosfet (as per following image), whereas (for example) signal driver of up left P mosfet linked to signal driver of down right P mosfet, hence when this link set to high (or low) both FET turn to high (or low)

my question is: Will the type C mosfet driver for all 4 h-bridge mosfets get a benefit from its fast switching performance? If they link together with a driver type of A or B they can not drive those linked mosfet with same logic

following schematic is the my preliminary design for using 2 pull-push gate driver for h-bridge circuit

Answer 1

No one pointed out the subtlety of type C. Note the PNP on the TOP, NPN on the BOTTOM. That is the correct way to drive a FET gate at its maximum speed.

Q29 amplifies the logic level signal.

Q11 and Q12 respectively pull the gate hard to the drive rail, or hard to the ground rail. Low impedance. It is the fastest switching topology, giving virtually unlimited gate charge, and unlimited gate DIS-charge. At this point, the gate resistance becomes critical. You also find out why they can be 2W or more on large FETs. If you have a scope, be empirical, i usually find 4.7R is ideal. Lower, it rings, higher, it rounds the slope off and starts getting HOT! :D

The "standard" schematic that almost everyone uses, with NPN on TOP, PNP on bottom, is a push pull AMPLIFIER. It is the default driver circuit and it is WRONG!

Switching speed is determined by the gain of the respective transistors, they are never hard saturated,and gate charge/discharge is limited. As the gate voltage rises, Vce reduces on the NPN and so does charge current. As the gate voltage falls, so does Vce on the PNP, and discharge current. The Bases may be hard driven, but the current path for the Gate capacitance is severely restricted as the voltage across the transistor is insufficient. They also produce crossover distortion and have a nasty knee at half the rail voltage... They burn FETs out once you start pushing the speeds up. They are an AMPLIFIER, not a SWITCH.

All FET drivers, although they use FETs instead of transistors, run the PNP (Pchannel) on TOP.

Transistors have an issue... Base current. The Bases have to be pulled to the rails for it to work, its like you need a driver for the driver, lol... thats the purpose of Q29 and its pullup.

Or... Use driver chips and forget about it :)

Yes, it works on Pchannel FETs as well, as long as you bear in mind it requires inverting. +VE <--> -VE. PNP <--> NPN.

Just my two cents worth, take it or leave it. Precise switching is always a plus in Hbridge drivers ;)

Answer 2

Your question has changed substantially from its original form that I wrote this answer for as it as being closed. The answer below only addresses driving a high side P channel MOSFET using what you call your "push-pull" circuit that you originally posted:

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You sortof have the right idea of how to drive a high side P channel FET, but missed some details:

1. There is nothing limiting the voltage swing of the gate to the valid range. 24 V is too much for many FETS.

2. Get rid of R95. I can't even guess what purpose you think it serves. It will only slow down the response.

Here is a better circuit using your basic concept:

This circuit is for when the power supply is at least a few volts more than the desired FET gate swing.

Instead of operating Q1 as a switch, it is a controlled current sink. With 3.3 V on the base, there is about 2.6 V across R1. That means the current thru R1 is 9.6 mA. Most of which comes from the collector. Therefore, when the digital signal is low, Q1 is off. When high, Q1 sinks a bit over 9 mA, regardless of the power voltage.

9 mA thru 2 kΩ would result in 18 V. The Zener diode D1 will limit this to 12 V. 12 V across R2 results in 6 mA. The remaining 3+ mA flows thru D1, clipping the voltage to a safe level for the gate. Most FETs are fine with 12 V on the gate, but as always, check the datasheet for the particular FET you are using.

The remaining transistors, Q2 and Q3, are a impedance buffer at the expense of losing about 700 mV at each end. The 2 kΩ impedance of R2 together with the FET gate capacitance would result in slow rise and fall times. The double emitter follower buffer reduces that 2 kΩ impedance by the gain of the transistors. If the gain is 100, for example, then the FET gate is driven with about 20 Ω. That's much better.

Generally the 700 mV loss at each end doesn't matter, but you should consider it. With a 12 V zener, that means the gate is driven to 11.3 V instead of 12 V. Most FETs are specified with good R_DSON at 10 V, but check your datasheet. On the other end, 700 mV should be well below where the FET does much of anything, but again, check the datasheet.

It is a good idea to put a pullup resistor on the gate so that the gate floats to 0 V eventually. That also helps with startup.

Answer 3

I would suggest Olin's second circuit with a few changes. I would not use D1, instead i will make R1 100R and R2 470R. These changes will give me, 26mA on R1, and about 12V across R2. 26mA on the bases of Q2 and Q3 will give you more cuurent to the FET gate.

Answer 4

The original circuit above doesn't work. There is a mistake. The P Mosfet channel needs VGS negative. Like, VGS=-10V. The source is conected at +24V and VDD = 12V. When Q44 is ON, VG=+12V and Vs=+24V, so VGS Q47=-12V. It does Q47 run (ON). But, when Q45 is ON, VG=0V and VS = +24V, then VGS of Q47=-24V. Q47 will be at ON state our damage because VGS more than -20V.