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To drive power MOSFET following circuits with different pros and cons has been used

type A

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type B

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type C

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type c which is called pull-pusher gate driver can used either P or N mosfet enter image description here

in h-bridge driver, mostly used type A and B for controlling one side P and N type mosfet (as per following image), whereas (for example) signal driver of up left P mosfet linked to signal driver of down right P mosfet, hence when this link set to high (or low) both FET turn to high (or low)

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my question is: Will the type C mosfet driver for all 4 h-bridge mosfets get a benefit from its fast switching performance? If they link together with a driver type of A or B they can not drive those linked mosfet with same logic

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following schematic is the my preliminary design for using 2 pull-push gate driver for h-bridge circuit

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  • \$\begingroup\$ Research how FET based half and full bridge drivers work with deadtime and update your skills. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 11 '18 at 16:02
  • \$\begingroup\$ @NickAlexeev thanks for your note but this schematic just for demonstrate pull-push driver and it is obviously not completed for whole h-bridge the main question is how to use 4 pull-push circuit for 4 mosfet in h-bridge (I already know other circuit) \$\endgroup\$ – Hamid s k Sep 11 '18 at 16:04
  • \$\begingroup\$ @NickAlexeev I rephrase my question , hope it is more cleared and explained \$\endgroup\$ – Hamid s k Sep 11 '18 at 19:52
  • \$\begingroup\$ I've reopened the question. There is still a questionable feature (bug?) in your diagram for push-pull (the type C). The push-pull BJT pair is connected to +V_DRIVE in your diagram. It's altight for driving an N-channel MOSFET. However, what would happen if you have V_DRIVE=+12V, V_LOAD=+24V, and you try to drive a P-channel MOSFET? (Notice that the push-pull BJT pair is connected to V_LOAD in the black&white application note diagram.) \$\endgroup\$ – Nick Alexeev Sep 11 '18 at 20:26
  • \$\begingroup\$ @NickAlexeev those images are from some references and application note and demonstrate different circuit,that can drive mosfets , also image number 5 is belong to opensource h-bridge driver which used not type c to drive all 4 P & N mosfet . I've tried to modified that schematic with pull-push driver for all mosfets ,but have noticed I couldn't linked (for example) top left p type mosfet to button right n type mosfet with pull push driver , because when set this connected line to high ( or low) logic level , one of them turn on and other turn off whereas suppose to both turn on , or off \$\endgroup\$ – Hamid s k Sep 12 '18 at 4:57
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Your question has changed substantially from its original form that I wrote this answer for as it as being closed. The answer below only addresses driving a high side P channel MOSFET using what you call your "push-pull" circuit that you originally posted:


You sortof have the right idea of how to drive a high side P channel FET, but missed some details:

  1. There is nothing limiting the voltage swing of the gate to the valid range. 24 V is too much for many FETS.

  2. Get rid of R95. I can't even guess what purpose you think it serves. It will only slow down the response.

Here is a better circuit using your basic concept:

This circuit is for when the power supply is at least a few volts more than the desired FET gate swing.

Instead of operating Q1 as a switch, it is a controlled current sink. With 3.3 V on the base, there is about 2.6 V across R1. That means the current thru R1 is 9.6 mA. Most of which comes from the collector. Therefore, when the digital signal is low, Q1 is off. When high, Q1 sinks a bit over 9 mA, regardless of the power voltage.

9 mA thru 2 kΩ would result in 18 V. The Zener diode D1 will limit this to 12 V. 12 V across R2 results in 6 mA. The remaining 3+ mA flows thru D1, clipping the voltage to a safe level for the gate. Most FETs are fine with 12 V on the gate, but as always, check the datasheet for the particular FET you are using.

The remaining transistors, Q2 and Q3, are a impedance buffer at the expense of losing about 700 mV at each end. The 2 kΩ impedance of R2 together with the FET gate capacitance would result in slow rise and fall times. The double emitter follower buffer reduces that 2 kΩ impedance by the gain of the transistors. If the gain is 100, for example, then the FET gate is driven with about 20 Ω. That's much better.

Generally the 700 mV loss at each end doesn't matter, but you should consider it. With a 12 V zener, that means the gate is driven to 11.3 V instead of 12 V. Most FETs are specified with good RDSON at 10 V, but check your datasheet. On the other end, 700 mV should be well below where the FET does much of anything, but again, check the datasheet.

It is a good idea to put a pullup resistor on the gate so that the gate floats to 0 V eventually. That also helps with startup.

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  • \$\begingroup\$ thanks @olin-lathrop for your advise , I hope you could check my last image win NAAND logic that enriched with your suggestion , but I might add I intend to use this bridge for voltage from 24 to 12 and that's reason I used a regulated 12 volt specifically for gate driving \$\endgroup\$ – Hamid s k Sep 12 '18 at 16:47
  • \$\begingroup\$ I'm little lost on your explanation about zener diode role, because I measure the voltage and its about 2.3 volt whereas I expected clipped 10 volt , also voltage of collector and emitter of Q1(2N3904) almost equal , so I should have identical ampere across resistor(R1, R2), but it is NOT \$\endgroup\$ – Hamid s k Sep 23 '18 at 14:51
  • \$\begingroup\$ The zener in my circuit limits the FET gate drive to a safe level. With a 12 V zener, the voltage of the gate will be about 11.3 V below the source when driving the FET on. The discrepancy between 12 V and 11.3 V is due to the B-E drop of Q3. \$\endgroup\$ – Olin Lathrop Sep 23 '18 at 14:56
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I would suggest Olin's second circuit with a few changes. I would not use D1, instead i will make R1 100R and R2 470R. These changes will give me, 26mA on R1, and about 12V across R2. 26mA on the bases of Q2 and Q3 will give you more cuurent to the FET gate.

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The original circuit above doesn't work. There is a mistake. The P Mosfet channel needs VGS negative. Like, VGS=-10V. The source is conected at +24V and VDD = 12V. When Q44 is ON, VG=+12V and Vs=+24V, so VGS Q47=-12V. It does Q47 run (ON). But, when Q45 is ON, VG=0V and VS = +24V, then VGS of Q47=-24V. Q47 will be at ON state our damage because VGS more than -20V.

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