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I need some help changing dynamically parameters of one module

I'm trying to extract part of network data that it comes from the top module and goes to the internal modules

In specific I have one internal module (field_extract) that receives 4 inputs: the clock, data(network data from the top module), a signal that indicates the start of frame (sof), vld (indicates that the data is valid) and two parameters one of them is how many bytes I want to extract from data and the OFFSET of these bytes from the start of frame, the parameter that I want to modify in execution time is the OFFSET

Also, this module has two outputs, one is field(the value extracted from the data) and vld(asserts when the data it was extracted)

Instantiation of this module looks like this:

field_extract
#
(
  .BYTES(1),
  .OFFSET(TYPE_OFFSET)
)
Type_extract
(
  .clk(clk),
  .data(data),
  .sof(sof),
  .vld(vld),

  .field(Type),
  .field_vld(Type_vld)
);

my question is how can I change "TYPE_OFFSET" depending on a variable parameters

What I mean with this is: I want to extract "Type" in certain OFFSET depending on certain values extracted from the frame in the past, so "Type" is not at the same position of the frame if the first part of the frame contains certain values something like this:

always @ (posedge clk) begin
   if (First_Message_Type == MESSAGE_TYPE_X) TYPE_OFFSET <= 50;
end 

I know that the last code is not possible because TYPE_OFFSET is a constant but here is the question again... there is any way to modify this constant in a time of execution?

I hope this has been clear Thanks for your time and help.

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Parameters are defined at synthesis time, you can't change them at run time based on signals. With that in mind, there are basically two options: either convert that parameter to a signal, or instantiate multiple copies of the module with different (constant) parameters, and then appropriately select which one to use.

Here is an example of doing that: https://github.com/alexforencich/verilog-ethernet/blob/14d8819cd31f569e18bd8574c9a8417d130472ca/rtl/eth_mac_10g_tx.v#L128, with the appropriate output selected here: https://github.com/alexforencich/verilog-ethernet/blob/14d8819cd31f569e18bd8574c9a8417d130472ca/rtl/eth_mac_10g_tx.v#L296.

There are advantages and disadvantages to each technique - converting a parameter to a signal may not be possible depending on how it is used, or it may result in generating a lot of additional logic. Multiple module instances can also result in a lot of logic, but perhaps less than converting a parameter to a signal, not to mention the toolchain can usually optimize redundant logic across multiple instances that have the same inputs. Or, you could write a more specialized module that is more specific to what you're trying to do.

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If you want something to change while your design is running then you will have to pass that information as a signal to the module. Remember that you are describing hardware rather than using a regular programming language, and think about how such features would actually be implemented in hardware.

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