Given a process node (e.g. TSMC's 16nm FinFET+) what is the maximum power per mm2 that a digital ASIC can draw?
Secondary question: Assuming liquid nitrogen cooling, what would be the bottleneck preventing the digital ASIC from drawing more power?
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This sounds like an "ask your foundry" question?
However, beyond self-heating, the next limits will be in your ability to get power into the chip in the first place with an acceptable resistive drop. How many pins does it have? Are they connected with bondwires, or is this a "flip chip" BGA? What about motherboard traces?
Assuming liquid nitrogen cooling, the maximum power is limited by the same factors that limit power at room temperature but the scale factors will change. The transistors will have a limit on their saturation current and they will still have some leakage current. The current density in the wires is still limited by electromigration concerns. The wires still have resistance. At high frequencies the wiring still has inductance and capacitance that are relevant.
Which of these factors will actually limit performance and power consumption at low temperature depends strongly on how the circuits are designed and what they are doing.