Why is dynamic CMOS faster than static CMOS? One reason is that the load capacitance is small. I can not understand how they are related to the speed of CMOS. Another reason is the lower number of transistors for only NMOS. Is there any reason which makes them move faster?


closed as unclear what you're asking by Bimpelrekkie, Dmitry Grigoryev, Sparky256, Finbarr, Lior Bilia Sep 14 '18 at 12:40

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    \$\begingroup\$ dynamic cmos is faster than static cmos You're confused with something because there is no such thing as "dynamic cmos" nor it there "static cmos". If you would replace "CMOS" with "RAM" your question could make sense. The rest of the question makes so little sense that I'm giving up. I understand you're new here and we're supposed to be nice to the newbees and I want to be but this question simply makes too little sense. \$\endgroup\$ – Bimpelrekkie Sep 12 '18 at 19:09
  • \$\begingroup\$ Welcome. Yes, please edit the question to make it more clear. \$\endgroup\$ – mike65535 Sep 12 '18 at 19:10
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    \$\begingroup\$ @Bimpelrekkie: Ah, you young kids! You never heard of dynamic logic? It's a real thing, in which node capacitances are used to store logic states for short periods of time rather than using active latches or flip-flops. Many early microprocessors used dynamic logic, which is why they had a minimum clock speed below which they would not operate correctly. \$\endgroup\$ – Dave Tweed Sep 12 '18 at 19:13
  • \$\begingroup\$ @DaveTweed No, I never heard of dynamic logic before. So I learned something new today :-) \$\endgroup\$ – Bimpelrekkie Sep 12 '18 at 19:52
  • \$\begingroup\$ Yeah it is dynamic logic but not dynamic cmos \$\endgroup\$ – user198345 Sep 13 '18 at 4:13

All other things being equal (e.g., at a given process "node"), dynamic logic uses far fewer transistors than static logic to achieve the same function. Therefore, a complex circuit requires significantly less chip area, interconnecting wires are shorter, and the whole thing can run a tad faster.

  • \$\begingroup\$ Dynamic logic may require a "reset" timing phase, before the combinatorial inputs are allowed to trigger state changes. \$\endgroup\$ – analogsystemsrf Sep 13 '18 at 4:58

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