I am working on a sensing device where the voltage of a floating node is dependent on the quantity to be sensed, as well as the net charge stored in the node. I would like the device to be only sensitive to the external physical quantity, and thereby reduce as much as possible the time-variation of charge on the floating node.
In a typical scenario with solid-state memory devices, you would have a MOSFET whose gate is insulated in all directions, and a control gate coupled capacitively to it (and possibly also charging it through tunneling). The floating gate potential induces a certain channel conductance which can be measured with additional circuitry around the MOSFET.
My problem is that the process I am using (TSMC 65nm) has very thin MOSFET gate dielectric, so there is a non-negligible leakage current (on the order of 100 pA) due to electron tunneling across the gate dielectric. The charge stored on the floating node would be on the order of pC so with such currents, the variation will be fairly large and this would provide very low retention.
Are there alternative known ways to measure a floating node potential while drawing as least current as possible from it? One possibility is of course to increase the dielectric thickness of the MOSFET (or its permittivity) but I am constrained with whatever values the process uses.