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Altera Cyclone IV EP4CE6E22 with a 50 MHz input clock.
I want to get 24 MHz out of the ALTPLL megafunction.
The requested multiplication/division settings are 12/25 but actual settings turn out to be 47/98 which doesn't get an exact 24 MHz output.

What is the reason for this limitation?

Does it have to do with achievable binary representations of fractions?
I guess it cannot generate 50*12 MHz internally so it should generate a lower frequency using a non-integer multiplexer and somehow divide by this non-integer multiplexer to lock to the input frequency.

(I've found an Altera PDF about calculating achievable division/multiplication factors, but it doesn't explain what is the reason behind this limitation.)

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There are several limits on PLLs. The main one is the VCO output frequency range. You need to pick divider values that will result in an in-range output frequency. Second is the PFD frequency range. This is the frequency range supported by the phase and frequency detector that drives the VCO control voltage. Usually it's the low frequency end of the PFD range that you have to worry about, you can't divide the reference below this frequency.

In the case of the Cyclone IV, the input clock frequency range (supported by the input pin and internal routing) is 5 MHz to 265-472.5 MHz, depending on the speed grade, the PFD range is 5 MHz to 325 MHz, and the VCO range is 600 MHz to 1300 MHz (see device handbook vol 3 page 1-24, table 1-25). So you need to pick divider values that work with these ranges.

According to the PLL block diagram, there are four different dividers, n, M, K, and Cn, where n, M, and Cn range from 1 to 512 and K is either 1 or 2. You need to pick these values such that Fout = (Fin / n * M) / K / Cn and Fin / n is in the PFD range and Fin / n * M is in the VCO range.

Interestingly, it looks like 50*12/25 should work if n=1, M=12, K=1, and Cn=25 as this has a PFD frequency of 50 MHz and a VCO frequency of 600 MHz. It will not work if n=25, M=12, K=1, and Cn=1, as this has a PFD frequency of 2 MHz and a VCO frequency of 24 MHz.

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  • \$\begingroup\$ Thank you for the great detailed answer! You're right, this output frequency is supported, my mistake was that I used a single ALTPLL block for 2 different output frequencies and apparently this involves resource sharing between the 2 and this limited the available range of output frequencies. \$\endgroup\$ – axk Sep 13 '18 at 23:33
  • \$\begingroup\$ Yeah, if you want to generate two frequencies from one PLL, you have to find a VCO frequency that you can divide down to both output frequencies. Depending on the frequencies you need, you may need to use two PLLs. \$\endgroup\$ – alex.forencich Sep 13 '18 at 23:36

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