Altera Cyclone IV EP4CE6E22 with a 50 MHz input clock.
I want to get 24 MHz out of the ALTPLL megafunction.
The requested multiplication/division settings are 12/25 but actual settings turn out to be 47/98 which doesn't get an exact 24 MHz output.
What is the reason for this limitation?
Does it have to do with achievable binary representations of fractions?
I guess it cannot generate 50*12 MHz internally so it should generate a lower frequency using a non-integer multiplexer and somehow divide by this non-integer multiplexer to lock to the input frequency.
(I've found an Altera PDF about calculating achievable division/multiplication factors, but it doesn't explain what is the reason behind this limitation.)