I am working through a weird problem. We are pin constrained on our FPGA and need to control a common bus. This was all fine and good as all the software was sequential, but now some requests will be coming in at the same time for devices, but will now have to be put into a queue.
How should I take care of making sure that everything gets shoved into a FIFO without priority and without dropping data? I've got the outer design complete for controlling everything up until the bottle-neck where everything gets shoved into the pipe before being granted access to our "bus". Some requests will take a long time to come in, but will do so concurrently from an FPGA whereas software commands will come in sequentially, but less predictably. If I don't care about the order in which I grant access to the "bus", what is the best way to pipe all of this information into a single FIFO under the assumption that some commands will be coming in at the same time without knowing how many there will be? I would like to avoid having to request/ack/grant if possible as I would like all of this to be taken care of by a single component that just receives a bunch of data and takes care of the complexity. What is the easiest way to accomplish this?