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Recently I have been working with the Analog Devices AD797 op-amp in LTspice, and have been getting poor performance from the amplifier when using a low-amplitude signal. This is my circuit in LTspice:enter image description here

The voltage source I am using is a sine wave at 40KHz with amplitude of .125 V, parallel capacitance of 3.4nF and series resistance of 4KΩ. I am trying to mimic the hydrophone that this circuit will eventually be an amplifier for, so these numbers aren't random. Also, I have set the gain of the amplifier so high because this circuit will eventually need to amplify voltages much lower than .125 V. I believe my problem is with the blocking capacitor / highpass filter I use on the output of the voltage source. Vin is consistently lower than the amplitude of the voltage source and V2 looks identical to Vin, except it has been shifted negatively by a few millivolts. The following screenshots are what I see in LTspice when simulating the circuit. enter image description here

enter image description here

The second image include the output of the amplifier, which reflects this negative shift of the input signal. I am a relative beginner, and my understanding of reactive circuits is shaky. Any help with eliminating / minimizing this negative shift between Vin and V2 would be much appreciated. Thanks

Here is a link to the AD797 datasheet. http://www.analog.com/media/en/technical-documentation/data-sheets/AD797.pdf

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    \$\begingroup\$ Change the gain to 100 or 50 and see what happens to the shift \$\endgroup\$
    – Voltage Spike
    Sep 14, 2018 at 4:48
  • \$\begingroup\$ Also you can get the latest version of LT spice and you won't have to import the analog spice files anymore. \$\endgroup\$
    – Voltage Spike
    Sep 14, 2018 at 4:51
  • \$\begingroup\$ It can be that the model is not that well written, don't know. You could try to use one of their datasheet offset cancellation schemes (or any other), and see what you're getting. You could also try to simulate with uic, to try to force the circuit to behave as if the universe has just started -- you might need a bit more simulation time. Side note: the caps at the sources do absolutely nothing, unless you add some series resistance to the sources, or caps. Better yet, delete the caps, and specify Rser=0.1 Cpar=100u, or similar, to your supplies. \$\endgroup\$ Sep 14, 2018 at 6:26
  • \$\begingroup\$ Your first image shows "green" as Vin. That curve is NOT possible and I'm pretty sure Spice isn't being used correctly to get it. You cannot have a "drifting" ideal voltage source. Your schematic shows an ideal voltage source and a wire coming off of it called Vin. That curve in the time plot isn't possible, given that schematic. Just out of curiosity, try plotting V(V1) and see if it matches. \$\endgroup\$
    – jonk
    Sep 14, 2018 at 6:39
  • \$\begingroup\$ Can you elaborate a little bit on why this isn't possible. What do you mean by "drifting." Also, Plotting V(V1) is the same as plotting the node I have labelled Vin, is it not? \$\endgroup\$
    – Saunders
    Sep 14, 2018 at 16:56

4 Answers 4

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Ordinarily, without the op-amp connected, C1 and R1 would indeed form a high-pass filter, removing any DC component of the input signal, leaving it with zero mean. However, with the op-amp in place, there is another DC component added due to the op-amp's input bias current of 0.25μA, shown on ammeter AM1 here:

schematic

simulate this circuit – Schematic created using CircuitLab

With or without an external input signal, this current must be drawn via R1, as shown on ammeter AM2. By Ohm's law, that causes a drop of \$V=0.25\mu A \times 100k\Omega = 25mV \$ across R1, which brings the op-amp's non-inverting input to −25mV, shown on voltmeter VM1.

This is a DC offset, part of the DC operating point (or "quiescent" voltage) present at all times, and which will be multiplied by the closed loop gain of the amplifier, as if it were part of the input signal. It will be multiplied by about 500, to produce a DC offset of about −12V at the output, about which the output signal will be centered. This accounts for the clipping you observed.

Since both inputs will tend to have very similar bias currents, we can mitigate this offset by ensuring that the inverting input bias current causes a similar voltage shift at the inverting input, to cancel the one at the non-inverting input:

schematic

simulate this circuit

I've inserted R4 to develop 25mV, just like R1 does, and as you can see, the output offset is greatly diminished. However, it's not zero, because that extra impedance in the path to the inverting input doesn't account for the impedance due to R2 and R3.

To entirely cancel the effect of input bias current, the impedance from voltage source to op-amp input must be identical, for both inputs. We can calculate the effective impedance of R2 and R3 by considering their Thevenin equivalent, in which their effective resistance is both resistances combined as if they were connected in parallel:

schematic

simulate this circuit

We may consider that all input bias current must pass through this Thevenin resistance \$R_{TH}\$, and also R4. Their combined resistance must be equal to R1, for them to develop the same 25mV from 0.25μA of current:

$$ \begin{aligned} R_4 + R_{TH} &= R_1 \\ \\ R_4 &= R_1 - R_{TH} \\ \\ R_4 &= 100k\Omega - 998\Omega \\ \\ &\approx 99k\Omega \end{aligned} $$

schematic

simulate this circuit

This doesn't have anything to do with input offset voltage for the op-amp. That's a different problem entirely.

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The voltage offset of this amplifier is 80uV max (for the A grade part), if you have a gain of 500 I would expect 40000uV or 40mV. The B grade part is 60uV max for a total of 30000uV or 30mV which would be right on par for your simulation. If this is not acceptable, then maybe another part might be better. Or typically with gains like this an amp like this can serve as a pre-amp with a follower stage to pick up the rest of the gain.

enter image description here

Another thing that might be useful is an inverting configuration with trim adjustment.

enter image description here Source: https://wiki.analog.com/university/courses/electronics/text/chapter-3

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  • \$\begingroup\$ I quickly changed the gain in LTspice, and saw no change in the negative voltage shift. Any other suggestions? When I eliminated the resistor and capacitor with a single resistor (I know this isn't practical but I did it for the sake of testing) the drop all but disappears, and is replaced by a tiny difference between the signals which appears to be much closer to the offset voltage of 60-80 uV. Any other suggestions about the highpass filter I'm using and why it appears to be causing trouble? \$\endgroup\$
    – Saunders
    Sep 14, 2018 at 5:46
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I see 2 major problems, somewhat related. First of all 501 x .125 = 62.625. That is equal to 62.625 volts (sine) at the output. Not going to happen with +/-9 volts for power. You MUST divide gain by 10 to get a more rational 6.2625 volts at the output.

The clipped waveform is due to a saturated output. It is being over driven by your current gain setting.

Second thing I do not see is bypass capacitors for the power supply. You need to have 100nF smd capacitors at the IC power pins to the ground plane, along with 47uF capacitors within 1" or 25mm of the IC. It will ring and oscillate without proper bypass capacitors. They are cheap so cost is not an issue.

Correct any DC offsets after you have fixed these other problems.

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  • \$\begingroup\$ The clipping is anticipated. I am not actually trying to get an output of 60 V but instead be able to sufficiently amplify a weak hydrophone signal to a level where it can be passed to an ADC. This system will eventually end up on an ROV, so the distance to the sound source and thus the signal received by the hydrophone will vary. I am trying to design for the worst case of being very far away from the sound source and thus having a weak signal. Also there are bypass caps, but they are 100pF instead of 100nF. Will change. Does anything look wrong with the RC? When gone offset is way less. \$\endgroup\$
    – Saunders
    Sep 14, 2018 at 5:53
  • \$\begingroup\$ Not sure how accurate LTspice is emulating real world conditions. RC issue makes no sense. \$\endgroup\$
    – user105652
    Sep 14, 2018 at 6:07
  • \$\begingroup\$ Yeah it seems very out of the blue to me. Could it be a grounding issue? Seems like something work breadboarding or soldering up \$\endgroup\$
    – Saunders
    Sep 14, 2018 at 6:09
  • \$\begingroup\$ Breadboarding is NOT good for high voltage, high currents, high impedance, high frequencies or high gain. \$\endgroup\$
    – user105652
    Sep 14, 2018 at 6:13
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You could have potentially up to 3uA of bias current. For simplicity, we'll assume 1uA.

The negative input, with its 1k to ground, will see a 1mV offset inspired by the bias current. The positive input, with 100K to ground, will see 100mV, for a difference of 99mV.

With your gain of 500, that 99mV offset on the input becomes 49.5V on the output.

Try replacing R1 with a 1K and it should be better. This will give you a high-pass corner of about 160Hz unless you increase C1.

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  • \$\begingroup\$ I agree about the massive input bias current on that opamp. It is old (Its datasheet is 31 years old) and its very high input current reduces noise. A modern audio opamp has Jfet inputs and will work fine in this circuit. \$\endgroup\$
    – Audioguru
    Jan 3, 2023 at 17:18
  • \$\begingroup\$ True, but balancing the DC input impedances will help in either case. There's also a good case to be made for keeping your gain to 20-30dB per stage, particularly with an old part like this, but the input offset error is far more glaring here. \$\endgroup\$ Jan 3, 2023 at 20:40

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