Back in the 1970s, Texas Instruments had a now-discontinued range of products that they called GRAM (and read only equivalent GROM) which was basically a standard memory chip with address and data all multiplexed onto 8 pins. You'd start an operation by sending the chip two bytes of address and then every time you pulsed either the read or write pin it would read or write a byte using the bus, then increment the internal address counter. The result was a memory chip that was almost as fast (at least for sequential access operations) as a standard parallel memory chip, but which only need a 16-pin package, rather than the 28-pin packages other similar memories of the day needed.

Today, for similar applications, you'd probably most often use SPI-accessed serial memory -- but the problem is that such memories are quite slow (most have a maximum throughput of about 20Mbit/s; some run as fast as twice that, but I haven't found any faster than that) whereas a modern equivalent of those TI parts could be much faster than that, easily allowing 100+Mbit/s access.

Does anything exist that's still in production and which behaves similarly to those TI chips? The closest I can find today are custom-purpose parts, e.g. the VLSI VS23S010D, which combines a memory device that supports the kind of interface I'm looking for along with a display driver, which puts the pin count up to 48 pins... I'm ideally looking for something in a 14 or 16 pin package (I think 14 is the realistic minimum - 2x power, 8x data, clock, address select, read byte, write byte).

  • The MC68HC11 microcontroller had an annoying multiplexed address+data bus similar to what you describe, such a memory would be awesome for that. – pipe Sep 14 at 12:16
  • but the 68HC11 only muxed A0..7; A8..15 were still separate pins. – amI Sep 14 at 17:56
up vote 18 down vote accepted

The appropriate standard solution is probably QSPI (also called QPI, or also SQI). It is somewhat an extension of the SPI interface, but uses four (quad, hence the Q in the acronym) data bits (IO0/IO1/IO2/IO3) instead of a single signal for each direction (MISO/MOSI).

So the chips are very small (typically SO-8), and the interface is very efficient: you need to send the address for each read or write command, but then you can read multiple bytes in burst, four bit at each clock cycle. Max clock speed is typically ~104MHz for flash. It can be made even faster using a Dual Data Rate signaling (four bits at each clock edge, both rising and falling: so eight bits at each clock cycle - typically, flash chips will max out at 80MHz in this mode).

The chip datasheets will provide all details about the exact meaning/usage of each signal. To illustrate, here is a read command timing diagram (in single data rate mode, and taken from this datasheet):

enter image description here

Here, you see you need 14 clock cycles to get the first byte (at 80MHz, it means 175ns access time). But if you need more bytes, just add 2 cycles per byte (25ns). So reading in burst will make it much faster than a typical 70ns or even a 45ns flash parallel chip.

You can easily find NOR flash parts from a lot of manufacturers, using this interface. Note that their performances (max speed, dummy cycles count) and features (Quad i/O or just Dual I/O, DDR support) will vary, so check the datasheet.

RAM is a bit more difficult to find, but still available, notably from Microchip (e.g. 23LC512), ON semi (e.g. N01S818HA) and ISSI (e.g. IS62WVS2568GBLL-45). They are slower than flash, though. But the ISSI I suggest above still goes up to 45MHz (single data rate) with apparently a minimum read cycle needing 11 clocks for the first byte. Or put in another way: 200ns + 45ns per byte (180Mbit/s throughput), which is not bad, and exceeds the GRAM speed you indicated.

Also, note that a lot of high-end MCUs (from NXP, ST, ...) support this interface in hardware.

  • Yes, this looks like exactly what I was after. Thanks. :) – Jules Sep 14 at 11:40
  • Another pretty similar interface is the 4-bit SD bus. – Dmitry Grigoryev Sep 14 at 13:49
  • @DmitryGrigoryev That's right. But I don't think you can find RAM chips adhering to this, though. Likely there are only NAND flash chips (eMMC). – dim Sep 14 at 14:08
  • @dim -- my understanding (based on ST's QSPI interfaces) is that they are read/write (not just read only) -- RAM vs Flash shouldn't matter much either – ThreePhaseEel Sep 14 at 16:14
  • @ThreePhaseEel You're right: on ST chips, the QSPI interface can be set in one of two modes: indirect mode (you trigger commands to the chip by setting some registers explicitly), and memory-mapped mode (the flash interface automatically translates memory accesses into read commands). In memory-mapped mode, the reference manual explicitly says only reading is allowed. In indirect mode, however, you can send whatever command you want (read/write/whatever else), as you mentioned. I'll edit accordingly. – dim Sep 14 at 18:52

I'm posting this as another answer because it is something totally different.

There is another, but less common, interface that also nicely fits your description: HyperBus, designed by Cypress (it's proprietary).

This one uses DDR at much higher speeds (up to 166MHz), and a 8-bit bus. So you can reach 2666 Mbit/s (wow!), which leaves QSPI far behind. It is also designed for higher-density DRAM rather than SRAM, so you can find 8M x 8 chips (vs 256k x 8 for the ISSI QSPI SRAM mentioned in the other post). It uses only 12 signals (supply voltages excluded).

Here is a HyperRAM product from ISSI: IS66WVH8M8ALL. There are also HyperFlash products you can find.

But we are on another category of products. It is more expensive, less easily sourceable, chips are typically BGA, and the interface is a bit more complex (due to high speed and DDR). Also, fewer MCUs support this.

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