I'm trying to build my first two-layer PCB layout using this example schema:

enter image description here

I'm using SMD elements, which I would place on the top layer. Also I would create a ratsnet area as GND on the top layer.

I would create some ratsnet area for the SW pin, the output inductor pins and the boost capacitor pins. In that areas I would put some vias and connect them with a ratsnet on the bottom layer.

I'm not quite sure if this is correct so far or if I misunderstood the example. Because then I do not understand the 'additional vias on the GND' of the capacitors.

If the GND area should be on the bottom layer, what about the trace from the SW-pin?

  • 1
    What do you mean by a "ratsnest area"? Usually the "ratsnest" are the lines your CAD tool shows to indicate connections that haven't been made yet. There shouldn't be any ratsnest left when the design is complete. – The Photon Sep 14 at 18:02
  • @ThePhoton I'm using Eagle CAD. Drawing a polygon and then use 'ratsnet' – user3142695 Sep 14 at 18:24
  • why nor run the trace from cboost to sw under the chip? – Jasen Sep 14 at 23:34
up vote 8 down vote accepted

I'm not quite sure if this is correct so far or if I misunderstood the example. Because then I do not understand the 'additional vias on the GND' of the capacitors.

Vias have inductance, with a few nH each (depending on the size and this can be calculated). If you parallel vias, you are also paralleling their inductance and so by doubling vias, you half the inductance. Parasitic inductance creates further losses and lower rise times in switching applications, so a decrease in inductance is a good thing. Vias also have a small amount of resistance also, so parallel vias also decreases the resistance.

If the GND area should be on the bottom layer, what about the trace from the SW-pin?

The trace from the SW pin would go on one of the internal layers or bottom layer if using a 4 layer design (SIG-GND-PWR-SIG). If you have a 4 layer stackup, the ground layer is probably on one of the internal planes (ideally).

If your using a 2 layer design then the SW trace would go on the bottom layer, and the GND would be on the top.

  • Oh, great. Thanks. So the vias in the ground are just put on the GND, they are not there to take the signal from one layer to another, right? Could you provide an example how to calculate which size I do need? – user3142695 Sep 14 at 18:23
  • The vias on the ground plane (for a two layer board) would go between the top components, and the ground layer. For a 4 layer board, I would pour a ground layer on the top layer AND have the vias go to the internal ground layer. As far as the trace goes, it has to go on a different layer than top or ground to route around the other traces, so you'll need vias there. (to go from top to internal or bottom for the boost capacitor trace). – laptop2d Sep 15 at 3:08
  • Here is a via calculator circuitcalculator.com/wordpress/2006/03/12/pcb-via-calculator on most pcbs the plating thickness is 1mil – laptop2d Sep 15 at 3:08
  • Another good thing to do is if you are unsure, there is an eval baord with all the layers in it: ti.com/general/docs/lit/… – laptop2d Sep 15 at 3:47
  • The scale might be a little different but you could use an 0603 or 0805 as a rule to figure out distances and estimate via sizes. – laptop2d Sep 15 at 3:48

I would put Gnd layer on both sides where ever there is not a signal. Connect the layers with vias named Gnd. Lots of Gnd coverage, lots of vias. More Gnd never hurt anything, and it's less copper to remove from the copper plated board.

I buy boards from iteadstudio.com regularly, I leave all Gnd on I can.

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