I'm trying to build my first two-layer PCB layout using this example schema:
I'm using SMD elements, which I would place on the top layer. Also I would create a ratsnet area as GND on the top layer.
I would create some ratsnet area for the SW pin, the output inductor pins and the boost capacitor pins. In that areas I would put some vias and connect them with a ratsnet on the bottom layer.
I'm not quite sure if this is correct so far or if I misunderstood the example. Because then I do not understand the 'additional vias on the GND' of the capacitors.
If the GND area should be on the bottom layer, what about the trace from the SW-pin?